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參數(shù)資料
| 型號： | ADC1038CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit Serial I/O A/D Converter with Analog Multiplexer |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 551K |
| 代理商： | ADC1038CIWM |
ADC1038 Functional Block Diagram
1.0 Pin Descriptions
C
CLK
The clock applied to this input controls the suc-
cessive approximation conversion time interval.
The clock frequency applied to this input can be
between 700 kHz and 4 MHz.
S
CLK
The serial data clock input. The clock applied to
this input controls the rate at which the serial
data exchange occurs and the analog sampling
time available to acquire an analog input volt-
age. The rising edge loads the information on
the DI pin into the multiplexer address shift reg-
ister (address register). This address controls
which channel of the analog input multiplexer
(MUX) is selected.
The falling edge shifts the data resulting from
the previous A/D conversion out on DO. CS and
OE enable or disable the above functions.
The serial data input pin. The data applied to
this pin is shifted by S
into the multiplexer
address register. The first 3 bits of data (A0–A2)
are the MUX channel address (see the Multi-
plexer Address/Channel Assignment tables).
The fourth bit (R/L ) determines the data format
of the conversion result in the conversion to be
DI
D
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