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參數(shù)資料
| 型號： | ADC1038CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit Serial I/O A/D Converter with Analog Multiplexer |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 551K |
| 代理商： | ADC1038CIWM |
1.0 Pin Descriptions
(Continued)
started. When R/L is low the output data format
is left-justified; when high it is right-justified.
When right-justified, six leading “0”s are output
on DO before the MSB information; thus the
complete conversion result is shifted out in 16
clock periods.
The data output pin. The A/D conversion result
(D0–D9) is output on this pin. This result can be
left- or right-justified depending on the value of
R/L bit shifted in on DI.
This pin is an output and indicates the status of
the internal successive approximation register
(SAR). When high, it signals that the A/D con-
version is in progress. This pin is set high after
the analog input sampling time (t
) and re-
mains high for 41 C
periods. When SARS
goes low, the output shift register has been
loaded with the conversion result and another
A/D conversion sequence can be started.
The chip select pin. When a low is applied to
this pin, the rising edge of S
shifts the data
on DI into the address register.
The output enable pin. When OE and CS are
both low the falling edge of S
shifts out the
previous A/D conversion data on the DO pin.
CH0–CH7 The analog inputs of the MUX. A channel input
is selected by the address information at the DI
pin, which is loaded on the rising edge of S
CLK
into the address register.
Source impedances (R
S
) driving these inputs
should be kept below 1 k
. If R
is greater than
1 k
, the sampled data comparator will not
have enough time to acquire the correct value of
the applied input voltage.
The voltage applied to these inputs should not
exceed V
or go below DGND or AGND by
more than 50 mV. Exceeding this range on an
unselected channel will corrupt the reading of a
selected channel.
V
REF+
The positive analog voltage reference for the ana-
log inputs. In order to maintain accuracy the volt-
age range of V
REF
(V
= V
REF+
V
REF
) is
2.5 V
to 5.0 V
and the voltage at V
REF+
cannot
exceed V
CC
+ 50 mV.
V
REF
The negative voltage reference for the analog in-
puts. In order to maintain accuracy the voltage at
this pin must not go below DGND and AGND by
more than 50 mV or exceed 40% of V
CC
(for V
CC
=
5V, V
REF
(max) = 2V).
V
CC
The power supply pin. The operating voltage range
of V
is 4.75 V
to 5.25 V
. V
should be by-
passed with 10 μF and 0.1 μF capacitors to digital
ground for proper operation of the A/D converter.
DGND,
AGND
The digital and analog ground pins. In order to main-
tain accuracy the voltage difference between these
two pins must not exceed 300 mV.
GND The digital and analog ground pin for the ADC1031.
DO
SARS
CS
OE
2.0 Functional Description
2.1 DIGITAL INTERFACE
The ADC1038 implement its serial interface via seven digital
control lines. There are two clock inputs for the ADC1038.
The S
controls the rate at which the serial data exchange
occurs and the duration of the analog sampling time window.
The C
controls the conversion time and must be continu-
ously enabled. A low on CS enables the rising edge of S
to shift in the serial multiplexer addressing data on the DI pin.
The first three bits of this data select the analog input chan-
nel (see the Channel Addressing Tables). The following bit,
R/L , selects the output data format (right-justified or
left-justified) for the conversion to be started. With CS and
OE low the DO pin is active (out of TRI-STATE
) and the fall-
ing edge of S
shifts out the data from the previous analog
conversion. When the first conversion is started the data
shifted out on DO is erroneous as it depends on the state of
the Parallel Load 16-Bit Shift Register on power up, which is
unpredictable.
The ADC1031 implements its serial interface with only four
control pins since it has only one analog input and comes in
an eight pin mini-dip package. The S
, C
, CS and DO
pins are available for the serial interface. The output data for-
mat cannot be selected and defaults to a left-justified format.
The state of DO is controlled by CS only.
2.2 OUTPUT DATA FORMAT
When R/L is low the output data format is left-justified; when
high it is right-justified. When right-justified, six leading “0”s
are output on DO before the MSB, and the complete conver-
sion result is shifted out in 16 clock periods.
2.3 CS HIGH DURING CONVERSION
With a continuous S
input, CS must be used to synchro-
nize the serial data exchange. A valid CS is recognized if it
occurs at least 100 ns (t
) before the rising edge of
S
, thus causing data to be input on DI. If this does not oc-
cur there will be an uncertainty as to which S
rising edge
will clock in the first bit of data. CS must remain low during
the complete I/O exchange. Also, OE needs to be low if data
from the previous conversion needs to be accessed.
2.3.1 CS LOW CONTINUOUSLY
Another way to accomplish synchronous serial communica-
tion is to tie CS low continuously and use SARS and S
to
synchronize the serial data exchange. S
can be disabled
low during the conversion time and enabled after SARS
goes low. With CS low during the conversion time a zero will
remain on DO until the conversion is completed. Once the
conversion is complete, the falling edge of SARS will shift
out on DO the MSB before S
is enabled. This MSB would
be a leading zero if right-justified or D9 if left-justified. The
rest of the data will be shifted out once S
is enabled as
discussed previously. If CS goes high during the conversion
sequence DO is put into TRI-STATE, and the conversion re-
sult is not affected so long as CS remains high until the end
of the conversion.
2.4 TYING S
CLK
and C
CLK
TOGETHER
S
and C
can be tied together. The total conversion
time will increase because the maximum clock frequency is
now 1 MHz. The timing diagrams and the serial I/O ex-
change time (10 S
cycles) remain the same, but the con-
version time (T
= 41 C
cycles) lengthens from a mini-
mum of 14 μs to a minimum of 41 μs. In the case where CS
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