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參數(shù)資料
| 型號： | ADC10662CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | RES 12-OHM 5% 0.25W 200PPM THK-FILM SMD-1206 TR-7-PA |
| 中文描述： | 2-CH 10-BIT FLASH/SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | SO-24 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 274K |
| 代理商： | ADC10662CIWM |
Functional Description
(Continued)
On the left side of the diagram is a string of seven resistors
connected between V
and V
. Six comparators com-
pare the input voltage with the tap voltages on this resistor
string to provide a low-resolution “estimate” of the input volt-
age. This estimate is then used to control the multiplexer that
connects the MSB Ladder to the sixteen comparators on the
right. Note that the comparators on the left needn’t be very
accurate; they simply provide an estimate of the input volt-
age. Only the sixteen comparators on the right and the six on
the left are necessary to perform the initial six-bit flash con-
version, instead of the 64 comparators that would be re-
quired using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB Lad-
der tap points will be connected to the sixteen comparators
on the right. For example, assume that the estimator deter-
mines that V
is between 11/16 and 13/16 of V
. The es-
timator decoder will instruct the comparator MUX to connect
the 16 comparators to the taps on the MSB ladder between
10/16 and 14/16 of V
. The 16 comparators will then per-
form the first flash conversion. Note that since the compara-
tors are connected to ladder voltages that extend beyond the
range indicated by the estimator circuit, errors in the estima-
tor as large as 1/16 of the reference voltage (64 LSBs) will
be corrected. This first flash conversion produces the six
most significant bits of data— four bits in the flash itself, and
2 bits in the estimator.
The remaining four LSBs are now determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second,
four-bit flash conversion is then decoded, and the full 10-bit
result is latched.
Note that the sixteen comparators used in the first flash con-
version are reused for the second flash. Thus, the multistep
conversion technique used in theADC10662 andADC10664
needs only a small fraction of the number of comparators
that would be required for a traditional flash converter, and
far fewer than would be used in a conventional half-flash ap-
proach. This allows the ADC10662 and ADC10664 to per-
form high-speed conversions without excessive power drain.
Applications Information
1.0 MODES OF OPERATION
The ADC10662 and ADC10664 have two basic digital inter-
face modes. Figure 1 and Figure 2 are timing diagrams for
the two modes. The ADC10662 and ADC10664 have input
multiplexers that are controlled by the logic levels on pins S
0
and S
when S /H goes low. Table 1 is a truth table showing
how the input channnels are assigned.
Mode 1
In this mode, the S /H pin controls the start of conversion.
S/H is pulled low for a minimum of 150 ns. This causes the
comparators in the “coarse” flash converter to become ac-
tive. When S /H goes high, the result of the coarse conver-
sion is latched and the “fine” conversion begins. After 360 ns
(typical), INT goes low, indicating that the conversion results
are latched and can be read by pulling RD low. Note that CS
must be low to enable S /H or RD. CS is internally “ANDed”
DS011192-12
FIGURE 3. Block Diagram of the Multistep Converter Architecture
www.national.com
9
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PDF描述 |
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| ADC10664CIWM | 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold |
| ADC10734 | 10-Bit Plus Sign Serial I/O A/D Converters with Mux,Sample/Hold and Reference(10位串行輸入/輸出帶MUX，采樣/保持和參考功能的A/D轉(zhuǎn)換器) |
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC10662CIWM/NOPB | 功能描述:IC ADC 10BIT 360 NS 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC10662CIWMX | 功能描述:IC ADC 10BIT 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC10662CIWMX/NOPB | 制造商:Texas Instruments 功能描述:ADC Single Pipelined 1.5Msps 10-bit Parallel 24-Pin SOIC W T/R |
| ADC10662CMJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
| ADC10664 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold |
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