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參數(shù)資料
| 型號： | ADC12441883 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| 中文描述： | 動態(tài)息審查自校準12位帶符號的A / D轉換器的采樣保持電路 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 274K |
| 代理商： | ADC12441883 |
2.0 Functional Description
(Continued)
Digital Control Inputs
A/D Function
CS
WR
RD
CAL
AZ
1
0
1
1
X
X
1
1
1
1
1
1
1
0
0
X
X
Start Conversion without Auto-Zero
Read Conversion Result without Auto-Zero
Start Conversion with Auto-Zero
Read Conversion Result with Auto-Zero
Start Calibration Cycle
Test Mode (DB2, DB3, DB5 and DB6 become active)
1
X
1
0
FIGURE 1. Function of the A/D Control Inputs
The table in Figure 1 summarizes the effect of the digital
control inputs on the function of the ADC12441. The Test
Mode, where RD is high and CS and CAL are low, is used
during manufacture to thoroughly check out the operation of
the ADC12441. Care should be taken not to inadvertently
be in this mode, since DB2, DB3, DB5, and DB6 become
active outputs, which may cause data bus contention.
2.2 RESETTING THE A/D
All internal logic can be reset, which will abort any conver-
sion in process. The A/D is reset whenever a new conver-
sion is started by taking CS and WR low. If this is done when
the analog input is being sampled or when EOC is low, the
Auto-Cal correction factors may be corrupted, therefore re-
quiring an Auto-Cal cycle before the next conversion. This is
true with or without Auto-Zero. The Calibration Cycle cannot
be reset once started. On power-up the ADC12441 auto-
matically goes through a Calibration Cycle that takes typi-
cally 1396 clock cycles. For reasons that will be discussed
in Section 3.7, a new calibration cycle needs to be started
after the completion of the automatic one.
3.0 Analog Considerations
3.1 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
between V
IN
and AGND), over which 4095 positive output
codes and 4096 negative output codes exist. The A-to-D
can be used in either ratiometric or absolute reference ap-
plications. The voltage source driving V
REF
must have a
very low output impedance and very low noise. The circuit in
Figure 2a is an example of a very stable reference that is
appropriate for use with the ADC12441. The simple refer-
ence circuit of Figure 2b may be used when the application
does not require low full scale errors.
In a ratiometric system, the analog input voltage is propor-
tional to the voltage used for the A/D reference. When this
voltage is the system power supply, the V
REF
pin can be
tied to V
CC
. This technique relaxes the stability requirement
of the system reference as the analog input and A/D refer-
ence move together maintaining the same output code for
given input condition.
TL/H/11017–19
*
Tantalum
**
Ceramic
FIGURE 2a. Low Drift Extremely Stable Reference Circuit
TL/H/11017–20
Errors without any trims:
25
§
C
b
40
§
C to
a
85
§
C
g
0.2%
g
0.024%
g
(/2
LSB
Full Scale
Zero
Linearity
g
0.075%
g
0.024%
g
(/2
LSB
FIGURE 2b. Simple Reference Circuit
11
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