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參數(shù)資料
| 型號： | ADC12441883 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| 中文描述： | 動(dòng)態(tài)息審查自校準(zhǔn)12位帶符號的A / D轉(zhuǎn)換器的采樣保持電路 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 274K |
| 代理商： | ADC12441883 |
AC Electrical Characteristics
(Continued)
Note 4:
The power dissipation of this device under normal operation should never exceed 169 mW (Quiescent Power Dissipation
a
TTL Loads on the digital
outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex. when any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
(maximum junction
temperature),
i
JA
(package junction to ambient thermal resistance), and T
A
(ambient temperature). The maximum allowable power dissipation at any temperature
is P
Dmax
e
(T
Jmax
b
T
A
)/
i
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
e
125
§
C, and the typical thermal
resistance (
i
JA
) of the ADC12441 with CMJ and CIJ suffixes when board mounted is 47
§
C/W.
Note 5:
Human body model, 100 pF discharged through a 1.5 k
X
resistor.
Note 6:
Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than
50 mV.
TL/H/11017–3
This means that if AV
CC
and DV
CC
are minimum (4.75 V
DC
) and V
b
is maximum (
b
4.75 V
DC
), full-scale must be
s
4.8 V
DC
.
Note 7:
A diode exists between AV
CC
and DV
CC
as shown below.
TL/H/11017–4
To guarantee accuracy, it is required that the AV
CC
and DV
CC
be connected together to a power supply with separate bypass filters at each V
CC
pin.
Note 8:
Accuracy is guaranteed at f
CLK
e
2.0 MHz. At higher and lower clock frequencies accuracy may degrade. See curves in the Typical Performance
Characteristics section.
Note 9:
Typicals are at T
J
e
25
§
C and represent most likely parametric norm.
Note 10:
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11:
Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See Figures 1b and 1c.)
Note 12:
The ADC12441’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
result in a repeatability uncertainty of
g
0.20 LSB.
Note 13:
If T
A
changes then an Auto-Zero or Auto-Cal cycle will have to be re-started (see the Typical Performance Characteristic curves).
Note 14:
After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15:
If the clock is asynchronous to the falling edge of WR an uncertainty of one clock period will exist in the interval of t
A
, therefore making the minimum
t
A
e
6 clock periods and the maximum t
A
e
7 clock periods. If the falling edge of the clock is synchronous to the rising edge of WR then t
A
will be exactly 6.5 clock
periods.
Note 16:
The CAL line must be high before a conversion is started.
Note 17:
The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18:
The ADC12441 reference ladder is composed solely of capacitors.
Note 19:
A Military RETS Electrical Test Specification is available on request. At time of printing the ADC12441CMJ/883 RETS complies fully with the
boldface
limits in this column.
TL/H/11017–5
FIGURE 1a. Transfer Characteristic
5
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADC12441CIJ | 功能描述:IC ADC 12BIT DYNAM TEST 28CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC12441CMJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| ADC12441CMJ/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 13-Bit |
| ADC12451 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| ADC12451883 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
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