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參數(shù)資料
| 型號： | ADC1251CMJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 301K |
| 代理商： | ADC1251CMJ |
1.0 Pin Descriptions
DV
CC
(24),
AV
CC
(4)
The digital and analog positive power supply
pins. The digital and analog power supply
voltage range of the ADC1251 is
a
4.5V to
a
5.5V. To guarantee accuracy, it is required
that the AV
CC
and DV
CC
be connected to-
gether to the same power supply with sepa-
rate bypass capacitors (10
m
F tantalum in
parallel with a 0.1
m
F ceramic) at each V
CC
pin.
The analog negative supply voltage pin. V
b
has a range of
b
4.5V to
b
5.5V and needs
bypass capacitors of 10
m
F tantalum in paral-
lel with a 0.1
m
F ceramic.
The digital and analog ground pins. AGND
and DGND must be connected together ex-
ternally to guarantee accuracy.
V
b
(5)
DGND (12),
AGND (3)
V
REF
(2)
The reference input voltage pin. To maintain
accuracy the voltage at this pin should not
exceed the AV
CC
or DV
CC
by more than
50 mV or go below
a
3.5 V
DC
.
The analog input voltage pin. To guarantee
accuracy the voltage at this pin should not
exceed V
CC
by more than 50 mV or go below
V
b
by more than 50 mV.
V
IN
(1)
CS (10)
The Chip Select control input. This input is
active low and enables the WR, RD and S/H
functions.
RD (23)
The Read control input. With both CS and RD
low the TRI-STATE output buffers are en-
abled and the INT output is reset high.
WR (7)
The Write control input. The conversion is
started on the rising edge of the WR pulse
when CS is low. When this control line is
used the end of the analog input voltage ac-
quisition window is internally controlled by the
ADC1251.
S/H (11)
The sample and hold control input. This con-
trol input can also be used to start a conver-
sion. With CS low the falling edge of S/H
starts the analog input acquisition window.
The rising edge of S/H ends the acquisition
window and starts a conversion.
CLKIN (8)
The external clock input pin. The typical clock
frequency range is 500 kHz to 6.0 MHz.
CAL (9)
The Auto-Calibration control input. When
CAL is low the ADC1251 is reset and a cali-
bration cycle is initiated. During the calibra-
tion cycle the values of the comparator offset
voltage and the mismatch errors in the ca-
pacitor reference ladder are determined and
stored in RAM. These values are used to cor-
rect the errors during a normal cycle of A/D
conversion.
AZ (6)
The Auto-Zero control input. With the AZ pin
held low during a conversion, the ADC1251
goes into an auto-zero cycle before the actu-
al A/D conversion is started. This Auto-Zero
cycle corrects for the comparator offset volt-
age. The total conversion time (t
C
) is in-
creased by 26 clock periods when Auto-Zero
is used.
EOC (22)
The End-of-Conversion control output. This
output is low during a conversion or a calibra-
tion cycle.
INT (21)
The Interrupt control output. This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches. Reading the
result or starting a conversion or calibration
cycle will reset this output high.
DB0/DB8–
DB7/DB12
(13–20)
The TRI-STATE output pins. Twelve bit plus
sign output data access is accomplished us-
ing two successive RDs of one byte each,
high byte first (DB8–DB12). The data format
used is two’s complement sign bit extended
with DB12 the sign bit, DB11 the MSB and
DB0 the LSB.
2.0 Functional Description
The ADC1251 is a 12-bit plus sign A/D converter with the
capability of doing Auto-Zero or Auto-Cal routines to mini-
mize zero, full-scale and linearity errors. It is a successive-
approximation A/D converter consisting of a DAC, compar-
ator and a successive-approximation register (SAR). Auto-
Zero is an internal calibration sequence that corrects for the
A/D’s zero error caused by the comparator’s offset voltage.
Auto-Cal is a calibration cycle that not only corrects zero
error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies. Auto-Cal minimizes the errors
of the ADC1251 without the need for trimming during its
fabrication. An Auto-Cal cycle can restore the accuracy of
the ADC1251 at any time, which ensures accuracy over
temperature and time.
2.1 DIGITAL INTERFACE
On power up, a calibration sequence should be initiated by
pulsing CAL low with CS and S/H high. To acknowledge the
CAL signal, EOC goes low after the falling edge of CAL, and
remains low during the calibration cycle of 1399 clock peri-
ods. During the calibration sequence, first the comparator’s
offset is determined, then the capacitive DAC’s mismatch
errors are found. Correction factors for these errors are then
stored in internal RAM.
A conversion can be initiated by taking CS and WR low. If
AZ is low an Auto-Zero cycle, which takes approximately 26
clock periods, is inserted before the analog input is sampled
and the actual conversion is started. AZ must remain low
during the complete conversion sequence. After Auto-Zero
the acquisition opens and the analog input is sampled for
approximately 7 clock periods. If AZ is high, the Auto-Zero
cycle is not inserted after the rising edge of WR. In this case
the acquisition window opens when the ADC1251 com-
pletes a conversion, signaled by the rising edge of EOC. At
the end of the acquisition window EOC goes low, signaling
that the analog input is no longer being sampled and that
the A/D successive approximation conversion has started.
11
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