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參數(shù)資料
| 型號(hào)： | ADC1251CMJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 301K |
| 代理商： | ADC1251CMJ |
3.0 Analog Considerations
(Continued)
3.5 INPUT BYPASS CAPACITORS
An external capacitor can be used to filter out any noise due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result.
3.6 INPUT SOURCE RESISTANCE
The analog input can be modeled as shown in Figure 6.
External R
S
will lengthen the time period necessary for the
voltage on C
REF
to settle to within
(/2
LSB of the analog
input voltage. With t
A
e
3.5
m
s, R
S
s
1 k
X
will allow a 5V
analog input voltage to settle properly.
3.7 POWER SUPPLIES
Noise spikes on the V
CC
and V
b
supply lines can cause
conversion errors as the comparator will respond to this
noise. The A/D is especially sensitive during the Auto-Zero
or -Cal procedures to any power supply spikes. Low induc-
tance tantalum capacitors of 10
m
F or greater paralleled
with 0.1
m
F ceramic capacitors are recommended for supply
bypassing. Separate bypass capacitors should be placed
close to the DV
CC
, AV
CC
and V
pins. If an unregulated
voltage source is available in the system, a separate
LM340LAZ-5.0 voltage regulator for the A-to-D’s V
CC
(and
other analog circuitry) will greatly reduce digital noise on the
supply line.
3.8 THE CALIBRATION CYCLE
On power up the ADC1251 goes through an Auto-Cal cycle
which cannot be interrupted. Since the power supply, refer-
ence, and clock will not be stable at power up, this first
calibration cycle will not result in an accurate calibration of
the A/D. A new calibration cycle needs to be started after
the power supplies, reference, and clock have been given
enough time to stabilize. During the calibration cycle, cor-
rection values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full scale,
offset, and linearity errors down to the specified limits. Full
scale error typically changes
g
0.2 LSB over temperature
and linearity error changes even less; therefore it should be
necessary to go through the calibration cycle only once af-
ter power up if Auto-Zero is used to correct the zero error
change. Since Auto-Zero cannot be activated with S/H con-
version method it may be necessary to do a calibration cy-
cle more than once.
3.9 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the
A/D, the Auto-Zero cycle can be used. It may be necessary
to do an Auto-Zero cycle whenever the ambient tempera-
ture changes significantly. (See the curve titled ‘‘Zero Error
Change vs Ambient Temperature’’ in the Typical Perform-
ance Characteristics.) A change in the ambient temperature
will cause the V
OS
of the sampled data comparator to
change, which may cause the zero error of the A/D to be
greater than
g
1 LSB. An Auto-Zero cycle will maintain the
zero error to
g
1 LSB or less.
4.0 Dynamic Performance
Many applications require the A/D converter to digitize AC
signals, but the standard DC integral and differential nonlin-
earity specifications will not accurately predict the A/D con-
verter’s performance with AC input signals. The important
specifications for AC applications reflect the converter’s
ability to digitize AC signals without significant spectral er-
rors and without adding noise to the digitized signal. Dynam-
ic characteristics such as signal-to-noise
a
distortion ratio
(S/(N
a
D)), effective bits, full power bandwidth, aperture
time and aperture jitter are quantitative measures of the
A/D converter’s capability.
An A/D converter’s AC performance can be measured us-
ing Fast Fourier Transform (FFT) methods. A sinusoidal
waveform is applied to the A/D converter’s input, and the
transform is then performed on the digitized waveform. S/
(N
a
D) is calculated from the resulting FFT data, and a
spectral plot may also be obtained. Typical values for S/
(N
a
D) are shown in the table of Electrical Characteristics,
and spectral plots are included in the typical performance
curves.
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can
be seen in the S/(N
a
D) versus frequency curves. These
curves will also give an indication of the full power band-
width (the frequency at which the S/(N
a
D) drops 3 dB).
TL/H/11024–22
FIGURE 6. Analog Input Equivalent Circuit
14
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