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參數(shù)資料
| 型號(hào)： | ADC12762 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 1.4 MHz, 300 mW A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 12位，1.4兆赫，300毫瓦的A / D輸入多路復(fù)用器和轉(zhuǎn)換器采樣/保持 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | ADC12762 |
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Connection Diagrams
Pin Descriptions
AV
CC
These are the two positive analog supply
inputs. They should always be con-
nected to the same voltage source, but
are brought out separately to allow for
separate bypass capacitors. Each supply
pin should be bypassed to AGND with a
0.1 μF ceramic capacitor in parallel with
a 10 μF tantalum capacitor.
This is the positive digital supply input. It
should always be connected to the same
voltage as the analog supply, AV
. It
should be bypassed to DGND2 with a
0.1 μF ceramic capacitor in parallel with
a 10 μF tantalum capacitor.
These are the power supply ground pins.
There are separate analog and digital
ground pins for separate bypassing of
the analog and digital supplies. The
ground pins should be connected to a
stable, noise-free system ground. All of
the ground pins should be returned to the
same potential. AGND is the analog
ground for the converter. DGND1 is the
ground pin for the digital control lines.
DGND2 is the ground return for the out-
put databus. See Section 6.0 LAYOUT
AND GROUNDING for more information.
These are the TRI-STATE output pins,
enabled by RD, CS, and OE.
These are the analog input pins to the
multiplexer. For accurate conversions,
no input pin (even one that is not se-
lected) should be driven more than 50
mV below ground or 50 mV above V
CC
.
DV
CC
AGND,
DGND1,
DGND2
DB0–DB11
V
IN1
, V
IN2
MUX OUT
This is the output of the on-board analog
input multiplexer.
This is the direct input to the 12-bit sam-
plingA/D converter. For accurate conver-
sions, this pin should not be driven more
than 50 mV below ground or 50 mV
above V
CC
.
This pin selects the analog input that will
be connected to the ADC12762 during
the conversion. The input is selected
based on the state of S0 when EOC
makes its high-to-low transition. Low se-
lects V
IN1
, high selects V
IN2
.
This pin should be tied to DGND1.
This is the active low Chip Select control
input. When low, this pin enables the RD,
S/H, and OE inputs. This pin can be tied
low.
This is the active low Interrupt output.
When using the Interrupt Interface Mode
(Figure 1), this output goes low when a
conversion has been completed and indi-
cates that the conversion result is avail-
able in the output latches. This output is
always high when RD is held low (Figure
2).
This is the End-of-Conversion control
output. This output is low during a con-
version.
This is the active low Read control input.
When RD is low (and CS is low), the INT
output is reset and (if OE is high) data
appears on the data bus. This pin can be
tied low.
ADC IN
S0
MODE
CS
INT
EOC
RD
DS012811-26
Top View
www.national.com
9
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