參數(shù)資料
型號: ADC12L032
廠商: National Semiconductor Corporation
元件分類: 串行ADC
英文描述: 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold(可自行校對3.3V12位串行輸入/輸出帶MUX,采樣/保持功能A/D轉換器)
中文描述: 3.3自校準12位帶符號串行I /辦公自動化/ D轉換器MUX和采樣/保持(可自行校對3.3V12位串行輸入/輸出帶復用,采樣/保持功能的A / D轉換器)
文件頁數(shù): 10/36頁
文件大小: 819K
代理商: ADC12L032
AC Electrical Characteristics
(Continued)
Thermal
Resistance
θ
JA
70C/W
64C/W
57C/W
50C/W
Part Number
ADC12L030CIWM
ADC12L032CIWM
ADC12L034CIWM
ADC12L038CIWM
Note 5:
The human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin.
Note 6:
See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7:
Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
+ or 5V below GND
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V
A
+ or below GND by more than 50 mV. As an example, if V
A
+ is 3.0 V
DC
, full-scale input voltage must be
3.05
V
DC
to ensure accurate conversions.
Note 8:
To guarantee accuracy, it is required that the V
A
+ and V
D
+ be connected together to the same power supply with separate bypass capacitors at each V
+
pin.
Note 9:
With the test condition for V
REF
(V
REF
+ V
REF
) given as +2.500V the 12-bit LSB is 610 μV and the 8-bit LSB is 9.8 mV.
Note 10:
Typicals are at T
J
= T
A
= 25C and represent most likely parametric norm.
Note 11:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12:
Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).
Note 13:
Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to +1 (see Figure 4).
Note 14:
Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15:
The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16:
Channel leakage current is measured after the channel selection.
Note 17:
Timing specifications are tested at the TTL logic levels, V
IL
= 0.4V for a falling edge and V
IH
= 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 18:
The ADC12L030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will
result in a maximum repeatability uncertainty of 0.2 LSB.
Note 19:
If SCLK and CCLK are driven from the same clock source, then t
A
is 6, 10, 18 or 34 clock periods minimum and maximum.
Note 20:
The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
DS011830-6
A
www.national.com
10
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