參數(shù)資料
型號(hào)： ADC12L032CIWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： ADC
英文描述： 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
中文描述： 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： SOP-20
文件頁(yè)數(shù)： 25/36頁(yè)
文件大?。?/td> 828K
代理商： ADC12L032CIWM
Application Hints
(Continued)
output during these instructions is from conversion N which
was started during I/O sequence 1. The Configuration Modi-
fication timing diagram describes in detail the sequence of
events necessary for a Data Out without Sign, Data Out with
Sign, or 6/10/18/34 CCLK Acquisition time mode selection.
Table 5 describes the actual data necessary to be input to
the ADC to accomplish this configuration modification. The
next instruction, shown in Figure 8 issued to the A/D starts
conversion N+1 with 8 bits of resolution formatted MSB first.
Again the data output during this I/O cycle is the data from
conversion N.
The number of SCLKs applied to the A/D during any conver-
sion I/O sequence should vary in accord with the data out
word format chosen during the previous conversion I/O se-
quence. The various formats and resolutions available are
shown in Table 1 In Figure 8 since 8-bit without sign MSB
first format was chosen during I/O sequence 4, the number
of SCLKs required during I/O sequence 5 is 8. In the follow-
ing I/O sequence the format changes to 12-bit without sine
MSB first; therefore the number of SCLKs required during
I/O sequence 6 changes accordingly to 12.
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that the ADC expects. Not do-
ing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below de-
tails out the number of clock periods required for different
DO formats:
Number of
SCLKs
Expected
8
9
12
13
16
17
DO Format
8-Bit MSB or LSB First
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
SIGN OFF
SIGN ON
12-Bit MSB or LSB First
16-Bit MSB or LSB first
If erroneous SCLK pulses desynchronize the communica-
tions, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.
The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continu-
ously vs. the case when CS is cycled. Take the I/O sequence
detailed in Figure 7 (Typical Power Supply Sequence) as an
example. The table below lists the number of SCLK pulses
required for each instruction:
Instruction
CS Low
Continuously
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
13 SCLKs
CS Strobed
Auto Cal
Read Status
Read Status
12-Bit + Sign Conv 1
12-Bit + Sign Conv 2
8 SCLKs
8 SCLKs
8 SCLKs
8 SCLKs
13 SCLKs
1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
for a particular A/D conversion (See Tables 2, 3, 4, 5). In Fig-
ure 8the only times when the channel configuration could be
modified would be during I/O sequences 1, 4, 5 and 6. Input
channels are reselected before the start of each new conver-
sion. Shown below is the data bit stream required on DI, dur-
ing I/O sequence number 4 in Figure 8 to set CH1 as the
positive input and CH0 as the negative input for the different
versions of ADCs:
Part
Number
DI Data
DI3
L
L
L
L
DI0
L
L
L
L
DI1
H
H
H
H
DI2
L
L
L
L
DI4
H
H
L
L
DI5
L
L
H
L
DI6
X
X
L
H
DI7
X
X
X
L
ADC12L030
ADC12L032
ADC12L034
ADC12L038
Where X can be a logic high (H) or low (L).
1.5 Power Up/Down
The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see Tables 5,
6 and the Power Up/Down timing diagrams). When the ADC
is powered down in this way the circuitry necessary for an
A/D conversion is deactivated. The circuitry necessary for
digital I/O is kept active. Hardware power up/down is con-
trolled by the state of the PD pin. Software power up/down is
controlled by the instruction issued to the ADC. If a software
power up instruction is issued to the ADC while a hardware
power down is in effect (PD pin high) the device will remain
DS011830-37
FIGURE 8. Changing the ADC’s Conversion Configuration
www.national.com
25
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