參數(shù)資料
型號(hào)： ADC12L032CIWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
中文描述： 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： SOP-20
文件頁(yè)數(shù)： 30/36頁(yè)
文件大?。?/td> 828K
代理商： ADC12L032CIWM
Application Hints
(Continued)
4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12L030/2/4/8’s fully differential ADC generate a
two’s complement output that is found by using the equa-
tions shown below:
for (12-bit) resolution the Output Code =
for (8-bit) resolution the Output Code =
Round off to the nearest integer value between 4096 to
4095 for 12-bit resolution and between 256 to 255 for 8-bit
resolution if the result of the above equation is not a whole
number.
Examples are shown in the table below:
Digital
Output
Code
V
REF+
V
REF
V
IN+
V
IN
+2.5V
+2.500V
+2.500V
+2.500V
+1V
0V
0V
0V
+1.5V
+2V
+2.499V
0V
0V
0V
0,1111,1111,1111
0,1100,1100,1101
1,1111,1111,1111
1,0000,0000,0000
+2.500V
+2.500V
5.0 INPUT CURRENT
At the start of the acquisition window (t
) a charging current
flows into or out of the analog input pins (A/DIN1 and
A/DIN2) depending on the input voltage polarity. The analog
input pins are CH0–CH7 and COM when A/DIN1 is tied to
MUXOUT1 andA/DIN2 is tied to MUXOUT2. The peak value
of this input current will depend on the actual input voltage
applied, the source impedance and the internal multiplexer
switch on resistance. With MUXOUT1 tied to A/DIN1 and
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 k
. The A/DIN1 and A/DIN2 mux
on resistance is typically 750
.
6.0 INPUT SOURCE RESISTANCE
For low impedance voltage sources (
<
600
), the input
charging current will decay, before the end of the S/H’s ac-
quisition time of 2 μs (10 CCLK periods with f
= 5 MHz), to
a value that will not introduce any conversion errors. For high
source impedances, the S/H’s acquisition time can be in-
creased to 18 or 34 CCLK periods. For less ADC resolution
and/or slower CCLK frequencies the S/H’s acquisition time
may be decreased to 6 CCLK periods. To determine the
number of clock periods (N
) required for the acquisition time
with a specific source impedance for the various resolutions
the following equations can be used:
12 Bit + Sign
N
C
= [R
S
+ 2.3] x f
C
x 0.824
8 Bit + Sign
N
C
= [R
S
+ 2.3] x f
C
x 0.57
Where f
C
is the conversion clock (CCLK) frequency in MHz
and R
is the external source resistance in k
. As an ex-
ample, operating with a resolution of 12 Bits+sign, a 5 MHz
clock frequency and maximum acquistion time of 34 conver-
sion clock periods the ADC’s analog inputs can handle a
source impedance as high as 6 k
. The acquisition time may
also be extended to compensate for the settling or response
time of external circuitry connected between the MUXOUT
and A/DIN pins.
The acquisition time (t
) is started by a falling edge of SCLK
and ended by a rising edge of CCLK (see Timing Diagrams).
If SCLK and CCLK are asynchronous one extra CCLK clock
period may be inserted into the programmed acquisition time
for synchronization. Therefore with asnychronous SCLK and
CCLK the acquisition time will change from conversion to
conversion.
7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 μF–0.1 μF) can be connected be-
tween the analog input pins, CH0–CH7, and analog ground
to filter any noise caused by inductive pickup associated with
long input leads. These capacitors will not degrade the con-
version accuracy.
8.0 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion er-
rors. Input filtering can be used to reduce the effects of the
noise sources.
9.0 POWER SUPPLIES
Noise spikes on the V
A+
and V
D+
supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 μF or greater
paralleled with 0.1 μF monolithic ceramic capacitors. More or
different bypassing may be necessary depending on the
overall system requirements. Separate bypass capacitors
should be used for the V
A+
and V
D+
supplies and placed as
close as possible to these pins.
10.0 GROUNDING
The ADC12L030/2/4/8’s performance can be maximized
through proper grounding techniques. These include the use
of separate analog and digital ground planes. The digital
ground plane is placed under all components that handle
digital signals, while the analog ground plane is placed under
all components that handle analog signals. The digital and
analog ground planes are connected together at only one
point, either the power supply ground or at the pins of the
ADC. This greatly reduces the occurence of ground loops
and noise.
Shown in Figure 16 is the ideal ground plane layout for the
ADC12L038 along with ideal placement of the bypass ca-
pacitors. The circuit board layout shown in Figure 16 uses
three bypass capacitors: 0.01 μF (C1) and 0.1 μF (C2) sur-
face mount capacitors and 10 μF (C3) tantalum capacitor.
11.0 CLOCK SIGNAL LINE ISOLATION
TheADC12L030/2/4/8’s performance is optimized by routing
the analog input/output and reference signal conductors as
far as possible from the conductors that carry the clock sig-
nals to the CCLK and SCLK pins. Ground traces parallel to
the clock signal traces can be used on printed circuit boards
to reduce clock signal interference on the analog input/
output pins.
www.national.com
30
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