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參數(shù)資料
| 型號： | ADC12L032CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 828K |
| 代理商： | ADC12L032CIWM |
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AC Electrical Characteristics
The following specifications apply for V
+
= V
+ = V
+ = +3.3 V
, V
+ = +2.500 V
, V
REF
= 0 V
DC
, 12-bit + sign conver-
sion mode, t
= t
= 3 ns, f
= f
= 5 MHz, R
= 25
, source impedance for V
+ and V
≤
25
, fully-differential input
with fixed 1.250V common-mode voltage, and 10(t
) acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note 10)
10
1
10
0
Limits
(Note 11)
5
Units
(Limits)
MHz (max)
MHz (min)
MHz (max)
Hz (min)
% (min)
% (max)
% (min)
% (max)
(max)
μs (max)
(max)
μs (max)
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
(min)
(max)
μs (min)
μs (max)
(max)
μs (max)
(max)
μs (max)
(min)
(max)
μs (min)
μs (max)
(max)
f
CK
Conversion Clock (CCLK) Frequency
f
SK
Serial Data Clock SCLK Frequency
5
Conversion Clock Duty Cycle
40
60
40
60
Serial Data Clock Duty Cycle
t
C
Conversion Time
12-Bit + Sign or 12-Bit
44(t
CK
)
44(t
CK
)
8.8
21(t
CK
)
4.2
6(t
CK
)
7(t
CK
)
1.2
1.4
10(t
CK
)
11(t
CK
)
2.0
2.2
18(t
CK
)
19(t
CK
)
3.6
3.8
34(t
CK
)
35(t
CK
)
6.8
7.0
4944(t
CK
)
988.8
76(t
CK
)
15.2
2(t
CK
)
3(t
CK
)
0.40
0.60
9(t
SK
)
8-Bit + Sign or 8-Bit
21(t
CK
)
t
A
Acquisition Time
(Note 19)
6 Cycles Programmed
6(t
CK
)
10 Cycles Programmed
10(t
CK
)
18 Cycles Programmed
18(t
CK
)
34 Cycles Programmed
34(t
CK
)
t
CAL
Self-Calibration Time
4944(t
CK
)
t
AZ
Auto-Zero Time
76(t
CK
)
t
SYNC
Self-Calibration or Auto-Zero
Synchronization Time
from DOR
2(t
CK
)
t
DOR
DOR High Time when CS is Low
Continuously
for Read Data and Software Power
Up/Down
CONV Valid Data Time
9(t
SK
)
1.8
μs (max)
t
CONV
8(t
SK
)
8(t
SK
)
1.6
700
(max)
μs (max)
μs (max)
t
HPU
Hardware Power-Up Time, Time from
PD Falling Edge to EOC Rising Edge
250
www.national.com
8
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| ADC12L032CIWMX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
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