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| 型號(hào)： | ADCLK854BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:12 48LFCSP |
| 設(shè)計(jì)資源： | Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，CMOS，HSTL，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 頻率 - 最大： | 1.2GHz |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 托盤(pán) |
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ADCLK854
Rev. 0 | Page 12 of 16
FUNCTIONAL DESCRIPTION
The ADCLK854 accepts a clock input from one of two inputs
and distributes the selected clock to all output channels. The
outputs are grouped into three banks of four and can be set to
either LVDS or CMOS levels. This allows the selection of mul-
tiple logic configurations ranging from 12 LVDS to 24 CMOS
outputs, along with other combinations using both types of logic.
CLOCK INPUTS
The ADCLK854 differential inputs are internally self-biased.
The clock inputs have a resistor divider that sets the common-
mode level for the inputs. The complementary inputs are biased
about 30 mV lower than the true input to avoid oscillations if
the input signal stops. See Figure 20 for the equivalent input
circuit.
The inputs can be ac-coupled or dc-coupled. Table 8 displays a
guide for input logic compatibility. A single-ended input can be
accommodated by ac or dc coupling to one side of the differential
input; bypass the other input to ground with a capacitor.
Note that jitter performance degrades with low input slew rate,
different termination schemes.
9k
9.5k
9k
10k
8.5k
VS
CLKx
GND
07
21
8-
02
0
Figure 20. ADCLK854 Input Stage
AC-COUPLED INPUT APPLICATIONS
The ADCLK854 offers two options for ac coupling. The first
option requires no external components (excluding the dc
blocking capacitor), it allows the user to simply couple the
reference signal onto the clock input pins. For more infor-
mation, see Figure 29.
The second option allows the use of the VREF pin to set the dc
bias level for the ADCLK854. The VREF pin can be connected to
CLKx and CLKx through resistors. This method allows lower
impedance termination of signals at the ADCLK854 (for more
information, see Figure 32). The internal bias resistors remain
in parallel with the external biasing. However, the relatively
high impedance of the internal resistors allows the external
termination to VREF to dominate. This method is also useful
when offsetting the inputs; using only the internal biasing, as
previously mentioned, is not desirable.
CLOCK OUTPUTS
Each driver consists of a differential LVDS output or two single-
ended CMOS outputs (always in phase). When the LVDS driver
is enabled, the corresponding CMOS driver is in tristate; when
the CMOS driver is enabled, the corresponding LVDS driver is
powered down and tristated. Figure 21 and Figure 22 display
the equivalent output stage.
OUTx
3.5mA
VS
3.5mA
07
21
8-
021
Figure 21. LVDS Output Simplified Equivalent Circuit
OUTA
VS
OUTB
VS
072
18
-02
2
Figure 22. CMOS Output Equivalent Circuit
Table 8. Input Logic Compatibility
Supply (V)
Logic
Common Mode (V)
Output Swing (V)
AC-Coupled
DC-Coupled
3.3
CML
2.9
0.8
Yes
Not allowed
2.5
CML
2.1
0.8
Yes
Not allowed
1.8
CML
1.4
0.8
Yes
3.3
CMOS
1.65
3.3
Not allowed
2.5
CMOS
1.25
2.5
Not allowed
1.8
CMOS
0.9
1.8
Yes
1.5
HSTL
0.75
Yes
LVDS
1.25
0.4
Yes
3.3
LVPECL
2.0
0.8
Yes
Not allowed
2.5
LVPECL
1.2
0.8
Yes
1.8
LVPECL
0.5
0.8
Yes
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| ADCLK854BCPZ-REEL7 | 功能描述:IC CLOCK BUFFER MUX 2:12 48LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類(lèi)型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ADCLK905 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Ultrafast SiGe ECL Clock/Data Buffers |
| ADCLK905/PCBZ | 功能描述:BOARD EVAL FOR ADCLK905 16LFCSP RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱(chēng):82EBV2081 |
| ADCLK905BCPZ-R2 | 功能描述:IC CLK/DATA BUFF DVR 1:1 16LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:SIGe 標(biāo)準(zhǔn)包裝:74 系列:- 類(lèi)型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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