ADF4001–SPECIFICATIONS1 (AVDD =" />
參數(shù)資料
型號(hào): ADF4001BRU-REEL
廠商: Analog Devices Inc
文件頁數(shù): 10/17頁
文件大?。?/td> 0K
描述: IC CLOCK GEN PLL 16-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘發(fā)生器(RF)
PLL:
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
REV.
–2–
ADF4001–SPECIFICATIONS1
(AVDD = DVDD = 3 V
10%, 5 V
10%; AVDD
≤ VP ≤ 6.0 V ; AGND = DGND =
CPGND = 0 V; RSET = 4.7 k ; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50
.)
Parameter
B Version
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
See Figure 3 for Input Circuit
RF Input Frequency
5/165
MHz min/max
RF Input Sensitivity
–10/0
dBm min/max
RF CHARACTERISTICS (5 V)
RF Input Frequency
10/200
MHz min/max
–5/0 dBm min/max
20/200
MHz min/max
–10/0 dBm min/max
REFIN CHARACTERISTICS
See Figure 2 for Input Circuit
REFIN Input Frequency
5/104
MHz min/max
For f < 5 MHz, Use DC-Coupled Square Wave
(0 to VDD)
REFIN Input Sensitivity
2
–5
dBm min
AC-Coupled. When DC-Coupled:
0 to VDD Max (CMOS Compatible)
REFIN Input Capacitance
10
pF max
REFIN Input Current
±100
A max
PHASE DETECTOR
Phase Detector Frequency
3
55
MHz max
CHARGE PUMP
ICP Sink/Source
Programmable: See Table V
High Value
5
mA typ
With RSET = 4.7 k
Low Value
625
A typ
Absolute Accuracy
2.5
% typ
With RSET = 4.7 k
RSET Range
2.7/10
k
typ
See Table V
ICP Three-State Leakage Current
1
nA typ
Sink and Source Current Matching
2
% typ
0.5 V
≤ V
CP
≤ V
P – 0.5
ICP vs. VCP
1.5
% typ
0.5 V
≤ VCP ≤ VP – 0.5
ICP vs. Temperature
2
% typ
VCP = VP/2
LOGIC INPUTS
VINH, Input High Voltage
0.8
× DVDD
V min
VINL, Input Low Voltage
0.2
× DV
DD
V max
IINH/IINL, Input Current
±1
A max
CIN, Input Capacitance
10
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
DVDD – 0.4
V min
IOH = 500
A
VOL, Output Low Voltage
0.4
V max
IOL = 500
A
POWER SUPPLIES
AVDD
2.7/5.5
V min/V max
DVDD
AVDD
VP
AVDD/6.0
V min/V max
AVDD
≤ V
P
≤ 6.0 V
IDD
4 (AI
DD + DIDD)
ADF4001
5.5
mA max
4.5 mA typical
IP
0.4
mA max
TA = 25
°C
Low Power Sleep Mode
1
A typ
NOISE CHARACTERISTICS
ADF4001 Phase Noise Floor
5
–161
dBc/Hz typ
@ 200 kHz PFD Frequency
–153
dBc/Hz typ
@ 1 MHz PFD Frequency
Phase Noise Performance6
@ VCXO Output
200 MHz Output
7
–99
dBc/Hz typ
@ 1 kHz Offset and 200 kHz PFD Frequency
Spurious Signals
200 MHz Output7
–90/–95
dBc typ/dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1Operating temperature range (B Version) is –40
°C to +85°C.
2AV
DD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS compatible levels.
3Guaranteed by design. Sample tested to ensure compliance.
4T
A = 25
°C; AV
DD = DVDD = 3 V; RFIN = 100 MHz.
5The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.
7f
REFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 200 MHz; N = 1000; Loop B/W = 20 kHz.
Specifications subject to change without notice.
B
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