參數(shù)資料
型號: ADF4157BCPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 12/24頁
文件大小: 0K
描述: IC PLL FREQ SYNTH 6GHZ 20LFCSP
標(biāo)準(zhǔn)包裝: 5,000
類型: 分?jǐn)?shù) N 合成器(RF)
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 6GHz
除法器/乘法器: 是/是
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 20-LFCSP-VQ
包裝: 帶卷 (TR)
ADF4157
Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
REVISION HISTORY
8/12—Rev. C to Rev. D
Changes to Figure 4 and Table 5......................................................6
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) .....22
Changes to Ordering Guide ...........................................................21
Criticizing
3/12—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Ordering Guide .......................................................... 21
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter ................................ 3
Changes to EPAD Note.................................................................... 6
1/09—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Reference Characteristics Parameter, Table 1 .......... 3
Changes to Table 3............................................................................ 5
Changes to Figure 4 and Table 5......................................................6
Changes to Figure 15...................................................................... 10
Changes to Figure 16...................................................................... 11
Changes to Figure 17...................................................................... 12
Changes to Figure 19...................................................................... 15
Added Negative Bleed Current Section, CLK Divider Mode
Section, and 12-Bit Clock Divider Value Section....................... 17
Changes to Reserved Bits Section and Figure 21 ....................... 17
Deleted Interfacing Section........................................................... 18
Added Fastlock Timer and Register Sequences Section,
Fastlock: An Example Section, and Fastlock: Loop Filter
Topology Section ............................................................................ 19
Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19
Added Operating with Wide Loop Filter Bandwidths
Section.............................................................................................. 20
Updated Outline Dimensions....................................................... 21
7/07—Revision 0: Initial Version
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