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參數(shù)資料
| 型號： | ADF4360-0BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 標準包裝： | 5,000 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 2.725GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
ADF4360-0
Data Sheet
Rev. C | Page 20 of 24
APPLICATIONS
FIXED FREQUENCY LO
Figure 17 shows the ADF4360-0 used as a fixed frequency LO at 2.6
GHz. The low-pass filter was designed using ADIsimPLL for a
channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz.
The maximum PFD frequency of the ADF4360-0 is 8 MHz.
Because using a larger PFD frequency allows users to use a smaller
N, the in-band phase noise is reduced to as low as possible,
–100 dBc/Hz. The 40 kHz bandwidth is chosen to be just greater
than the point at which the open-loop phase noise of the VCO is
–100 dBc/Hz, thus giving the best possible integrated noise. The
typical rms phase noise (100 Hz to 100 kHz) of the LO in this con-
figuration is 0.35°. The reference frequency is from a 16 MHz
TCXO from Fox; thus, an R value of 2 is programmed. Taking into
account the high PFD frequency and its effect on the band select
logic, the band select clock divider is enabled. In this case, a value of
8 is chosen. A very simple pull-up resistor and dc blocking capaci-
tor complete the RF output stage.
SPI
COMPATIBLE
SERIAL
BUS
ADF4360-0
VVCO
FOX
801BE-160
16MHz
VVCO
CPGND
AGND
DGND RF
OUTB
RFOUTA
CP
1nF
560pF
270pF
8.2nF
51
51
51
100pF
1nF
10
F
4.7k
1.5k
3k
RSET
CC
LE
DATA
CLK
REFIN
CN
VTUNE
DVDD AVDD CE MUXOUT
5
4
24
7
20
23
2
21
6
14
16
17
18
19
13
1
12
VVDD
LOCK
DETECT
04644-021
3
8
9
10
11
22
15
Figure 17. Fixed Frequency LO
INTERFACING
The ADF4360 family has a simple SPI-compatible serial inter-
face for writing to the device. CLK, DATA, and LE control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the appropriate register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz or
one update every 1.2 s. This is more than adequate for systems
that have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 18 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter. Because the ADuC812 is based
on an 8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three 8-
bit bytes from the MicroConverter to the device. When the
third byte has been written, the LE input should be brought
high to complete the transfer.
04644-022
ADuC812
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O PORTS
Figure 18. ADuC812 to ADF4360-x Interface
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and detect lock (MUXOUT configured as lock
detect and polled by the port input). When operating in the
described mode, the maximum SCLOCK rate of the ADuC812
is 4 MHz. This means that the maximum rate at which the out-
put frequency can be changed is 166 kHz.
ADSP-21xx Interface
Figure 19 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate fram-
ing. This provides a means for transmitting an entire block of
serial data before an interrupt is generated.
04644-023
ADSP-21xx
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
TFS
I/O PORTS
Figure 19. ADSP-21xx to ADF4360-x Interface
Set up the word length for 8 bits and use three memory loca-
tions for each 24-bit word. To program each 24-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
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| ADF4360-0BCPZRL7 | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
| ADF4360-1_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
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| ADF4360-1BCPRL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:INT. SYNTHESIZER & VCO - 2000 - 2550 MHZ - Tape and Reel |
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