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參數(shù)資料
| 型號： | ADF4360-0BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 標準包裝： | 5,000 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 2.725GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
ADF4360-0
Data Sheet
Rev. C | Page 10 of 24
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 13 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any sub-
sequent PD cycle.
The N-channel open-drain analog lock detect should be operat-
ed with an external pull-up resistor of 10 k nominal. When a
lock has been detected, this output is high with narrow low-
going pulses.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETECT
DGND
CONTROL
MUX
MUXOUT
DVDD
ANALOG LOCK DETECT
SDOUT
04644-013
Figure 13. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter,
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
Data Latch
C2
C1
0
Control Latch
0
1
R Counter
1
0
N Counter (A and B)
1
Test Mode Latch
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 14, to allow a wide frequency range
to be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at pow-
er-up. This sequence is
1. R counter latch
2. Control latch
3. N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
04644-014
0.5
0.7
0.9
1.1
1.3
1.5
1.9
2.1
2.3
1.7
2.5
VOLTAGE
(V)
FREQUENCY (MHz)
2200
2400
2600
2800
3000
Figure 14. Frequency vs. VTUNE, ADF4360-0
The R counter output is used as the clock for the band select logic
and should not exceed 1 MHz. A programmable divider is provid-
ed at the R counter input to allow division by 1, 2, 4, or 8 and is
controlled by Bits BSC1 and BSC2 in the R counter latch. Where
the required PFD frequency exceeds 1 MHz, the divide ratio should
be set to allow enough time for correct band selection.
After band select, normal PLL action resumes. The nominal
value of KV is 56 MHz/V or 28 MHz/V, if divide-by-2 operation
has been selected (by programming DIV2 [DB22] high in the N
counter latch). The ADF4360 family contains linearization cir-
cuitry to minimize any variation of the product of ICP and KV.
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| ADF4360-0BCPZRL7 | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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