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參數(shù)資料
| 型號(hào)： | ADF4360-0BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 2.725GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADF4360-0
Rev. C | Page 21 of 24
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm long-
er than the package lead length and 0.05 mm wider than the
package lead width. The lead should be centered on the pad to
ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that short-
ing is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 ounce
of copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
OUTPUT MATCHING
There are a number of ways to match the output of the
ADF4360-0 for optimum operation; the most basic is to use a
50 resistor to VVCO. A dc bypass capacitor of 100 pF is con-
nected in series, as shown in Figure 20. Because the resistor is
not frequency dependent, this provides a good broadband
match. The output power in this circuit typically gives 6.5
dBm output power into a 50 load.
100pF
04644-024
RFOUT
VVCO
50
51
Figure 20. Simple ADF4360-1 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match than a resistor and,
therefore, more output power. Additionally, a series inductor is
added after the dc bypass capacitor to provide a resonant LC
circuit. This tunes the oscillator output and provides approxi-
mately 10 dB additional rejection of the second harmonic. The
shunt inductor needs to be a relatively low value (<10 nH).
Experiments have shown that the circuit shown in Figure 21
provides an excellent match to 50 over the operating range of
the ADF4360-0. This gives approximately 4 dBm output power
across the frequency range of the ADF4360-0. Both single-ended
architectures can be examined using the EV-ADF4360-0EB1Z
evaluation board.
3.9nH
47nH
1.5pF
04644-025
RFOUT
VVCO
50
Figure 21. Differential ADF4360-0 Output Stage
If the user does not need the differential outputs available on
the ADF4360-0, the user may either terminate the unused out-
put or combine both outputs using a balun. The circuit in Figure 22
shows how best to combine the outputs.
1nH
3.6nH
47nH
3.6nH
1.5pF
10pF
1.5pF
50
1nH
RFOUTA
VVCO
RFOUTB
04644-026
Figure 22. Balun for Combining ADF4360-0 RF Outputs
The circuit in Figure 22 is a lumped-lattice-type LC balun. It is
designed for a center frequency of 2.6 GHz and outputs 1 dBm
at this frequency. The series 1 nH inductor is used to tune out
any parasitic capacitance due to the board layout from each
input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by 90°, thus
combining the two. The action of the 3.6 nH inductor and the
1.5 pF capacitor accomplishes this. The 12 nH is used to pro-
vide an RF choke to feed the supply voltage, and the 10 pF ca-
pacitor provides the necessary dc block. To ensure good RF
performance, the circuits in Figure 20 and Figure 22 are imple-
mented with Coilcraft 0402/0603 inductors and AVX 0402 thin-
film capacitors.
Alternatively, instead of the LC balun shown in Figure 22, both
outputs may be combined using a 180° rat-race coupler.
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| ADF4360-0BCPZRL7 | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
| ADF4360-1_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
| ADF4360-1BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP 制造商:Analog Devices 功能描述:PLL FREQ SYNTHESIZER SGL 24LFCSP EP - Trays 制造商:Analog Devices 功能描述:Analog Devices ADF4360-1BCP PLL 制造商:Analog Devices 功能描述:IC SYNTHESIZER PLL |
| ADF4360-1BCPRL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:INT. SYNTHESIZER & VCO - 2000 - 2550 MHZ - Tape and Reel |
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