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參數(shù)資料
| 型號： | ADG3304BCBZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 0K |
| 描述： | IC XLATOR 4CH 1.2/5.5V 12-WLCSP |
| 產(chǎn)品變化通告： | 8mm Carrier Tape Changes 28/Feb/2012 |
| 標準包裝： | 1 |
| 邏輯功能： | 變換器，雙向 |
| 位數(shù)： | 4 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 數(shù)據(jù)速率： | 50Mbps |
| 通道數(shù)： | 4 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 6ns |
| 電源電壓： | 1.15 V ~ 5.5 V |
| 工作溫度： | -25°C ~ 85°C |
| 封裝/外殼： | 12-UFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 12-WLCSP |
| 包裝： | 標準包裝 |
| 其它名稱： | ADG3304BCBZ-REEL7DKR |
Data Sheet
ADG3304
Rev. D | Page 15 of 20
TERMINOLOGY
VIHA
Logic input high voltage at Pin A1 to Pin A4.
VILA
Logic input low voltage at Pin A1 to Pin A4.
VOHA
Logic output high voltage at Pin A1 to Pin A4.
VOLA
Logic output low voltage at Pin A1 to Pin A4.
CA
Capacitance measured at Pin A1 to Pin A4 (EN = 0).
ILA, Hi-Z
Leakage current at Pin A1 to Pin A4 when EN = 0 (high
impedance state at Pin A1 to Pin A4).
VIHY
Logic input high voltage at Pin Y1 to Pin Y4.
VILY
Logic input low voltage at Pin Y1 to Pin Y4.
VOHY
Logic output high voltage at Pin Y1 to Pin Y4.
VOLY
Logic output low voltage at Pin Y1 to Pin Y4.
CY
Capacitance measured at Pin Y1 to Pin Y4 (EN = 0).
ILY, Hi-Z
Leakage current at Pin Y1 to Pin Y4 when EN = 0 (high
impedance state at Pin Y1 to Pin Y4).
VIHEN
Logic input high voltage at the EN pin.
VILEN
Logic input low voltage at the EN pin.
CEN
Capacitance measured at EN pin.
ILEN
Enable (EN) pin leakage current.
tEN
Three-state enable time for Pin A1 to Pin A4 and Pin Y1 to
Pin Y4.
tP, A→Y
Propagation delay when translating logic levels in the A→Y
direction.
tR, A→Y
Rise time when translating logic levels in the A→Y direction.
TF, A→Y
Fall time when translating logic levels in the A→Y direction.
DMAX, A→Y
Guaranteed data rate when translating logic levels in the A→Y
direction under the driving and loading conditions specified in
TSKEW, A→Y
Difference between propagation delays on any two channels
when translating logic levels in the A→Y direction.
tPPSKEW, A→Y
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the A→Y direction.
tP, Y→A
Propagation delay when translating logic levels in the Y→A
direction.
tR, Y→A
Rise time when translating logic levels in the Y→A direction.
tF, Y→A
Fall time when translating logic levels in the Y→A direction.
DMAX, Y→A
Guaranteed data rate when translating logic levels in the Y→A
direction under the driving and loading conditions specified in
tSKEW, Y→A
Difference between propagation delays on any two channels
when translating logic levels in the Y→A direction.
tPPSKEW, Y→A
Difference in propagation delay between any one channel and
the same channel on a different part (under the same driving/
loading conditions) when translating in the Y→A direction.
VCCA
VCCA supply voltage.
VCCY
VCCY supply voltage.
ICCA
VCCA supply current.
ICCY
VCCY supply current.
IHi-Z, A
VCCA supply current during three-state mode (EN = 0).
IHi-Z, Y
VCCY supply current during three-state mode (EN = 0).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADG3304BCPZ | 制造商:Analog Devices 功能描述: |
| ADG3304BCPZ-REEL | 制造商:Analog Devices 功能描述:LOW VOLTAGE 1.15 V TO 5.5 V, 4 CHANNEL, BIDIRECTIONAL, LOGIC - Tape and Reel |
| ADG3304BCPZ-REEL7 | 制造商:Analog Devices 功能描述:LOW VOLTAGE 1.15 V TO 5.5 V, 4 CHANNEL, BIDIRECTIONAL, LOGIC - Tape and Reel 制造商:Analog Devices 功能描述:ANAADG3304BCPZ-REEL7 1.2 V - 5.5 V, 4 CH |
| ADG3304BRU | 制造商:Analog Devices 功能描述:LOW VOLTAGE 1.2 V TO 5.5 V, BIDIRECTIONAL, LOGIC LEVEL TRANS - Bulk |
| ADG3304BRUZ | 功能描述:IC XLATOR 4CH 1.2/5.5V 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:- 標準包裝:1 系列:100ELT 邏輯功能:變換器 位數(shù):1 輸入類型:TTL 輸出類型:差分 數(shù)據(jù)速率:- 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/是 傳輸延遲（最大）:0.6ns 電源電壓:3 V ~ 3.8 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:Digi-Reel® 產(chǎn)品目錄頁面:1088 (CN2011-ZH PDF) 其它名稱:576-1360-6 |
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