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參數(shù)資料
| 型號： | ADG3304BCBZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XLATOR 4CH 1.2/5.5V 12-WLCSP |
| 產(chǎn)品變化通告： | 8mm Carrier Tape Changes 28/Feb/2012 |
| 標準包裝： | 1 |
| 邏輯功能： | 變換器，雙向 |
| 位數(shù)： | 4 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 數(shù)據(jù)速率： | 50Mbps |
| 通道數(shù)： | 4 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 6ns |
| 電源電壓： | 1.15 V ~ 5.5 V |
| 工作溫度： | -25°C ~ 85°C |
| 封裝/外殼： | 12-UFBGA，WLCSP |
| 供應商設備封裝： | 12-WLCSP |
| 包裝： | 標準包裝 |
| 其它名稱： | ADG3304BCBZ-REEL7DKR |
ADG3304
Data Sheet
Rev. D | Page 16 of 20
THEORY OF OPERATION
The ADG3304 level translator allows the level shifting
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, VCCA and
VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each
side of the device. When driving the A pins, the device translates
the VCCA-compatible logic levels to VCCY-compatible logic levels
available at the Y pins. Similarly, because the device is capable of
bidirectional translation, when driving the Y pins, the VCCY-
compatible logic levels are translated to VCCA-compatible logic
levels available at the A pins. When EN = 0, Pin A1 to Pin A4
and Pin Y1 to Pin Y4 are three-stated. When EN is driven high,
the ADG3304 goes into normal operation mode and performs
level translation.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3304 consists of four bidirectional channels. Each
channel can translate logic levels in either the A→Y or the Y→A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics. Figure 39 shows a
simplified block diagram of a bidirectional channel.
ONE-SHOT GENERATOR
6k
6k
Y
VCCA
VCCY
T2
T1
T3
T4
A
04860-053
P
N
U1
U2
U4
U3
Figure 39. Simplified Block Diagram of an ADG3304 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y→A direction is performed using Inverter U3
and Inverter U4. The one-shot generator detects a rising or
falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS
transistors (T1 to T2) for a rising edge, or the NMOS transistors
(T3 to T4) for a falling edge. This charges/discharges the
capacitive load faster, which results in faster rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding VCC rail (VCCA or VCCY) or to GND.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3304, the circuit that
drives the input of the ADG3304 channels should have an
output impedance of less than or equal to 150 and a
minimum peak current driving capability of 36 mA.
OUTPUT LOAD REQUIREMENTS
The ADG3304 level translator is designed to drive CMOS-
compatible loads. If current-driving capability is required, it is
recommended to use buffers between the ADG3304 outputs
and the load.
ENABLE OPERATION
The ADG3304 provides three-state operation at the A and Y
I/O pins by using the enable pin (EN), as shown in Table 5.
Table 5. Truth Table
EN
Y I/O Pins
A I/O Pins
0
Hi-Z1
1
Normal operation2
Normal operation2
1
High impedance state.
2
In normal operation, the ADG3304 performs level translation.
While EN = 0, the ADG3304 enters into three-state mode. In this
mode, the current consumption from both the VCCA and VCCY
supplies is reduced, allowing the user to save power, which is
critical, especially on battery-operated systems. The EN input pin
can be driven with either VCCA-compatible or VCCY-compatible
logic levels.
POWER SUPPLIES
For proper operation of the ADG3304, the voltage applied to
the VCCA must be less than or equal to the voltage applied to VCCY.
To meet this condition, the recommended power-up sequence
is VCCY first and then VCCA. The ADG3304 operates properly
only after both supply voltages reach their nominal values. It is
not recommended to use the part in a system where, during
power-up, VCCA can be greater than VCCY due to a significant
increase in the current taken from the VCCA supply. For
optimum performance, the VCCA pin and VCCY pin should be
decoupled to GND as close as possible to the device.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADG3304BCPZ | 制造商:Analog Devices 功能描述: |
| ADG3304BCPZ-REEL | 制造商:Analog Devices 功能描述:LOW VOLTAGE 1.15 V TO 5.5 V, 4 CHANNEL, BIDIRECTIONAL, LOGIC - Tape and Reel |
| ADG3304BCPZ-REEL7 | 制造商:Analog Devices 功能描述:LOW VOLTAGE 1.15 V TO 5.5 V, 4 CHANNEL, BIDIRECTIONAL, LOGIC - Tape and Reel 制造商:Analog Devices 功能描述:ANAADG3304BCPZ-REEL7 1.2 V - 5.5 V, 4 CH |
| ADG3304BRU | 制造商:Analog Devices 功能描述:LOW VOLTAGE 1.2 V TO 5.5 V, BIDIRECTIONAL, LOGIC LEVEL TRANS - Bulk |
| ADG3304BRUZ | 功能描述:IC XLATOR 4CH 1.2/5.5V 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 變換器 系列:- 標準包裝:1 系列:100ELT 邏輯功能:變換器 位數(shù):1 輸入類型:TTL 輸出類型:差分 數(shù)據(jù)速率:- 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無/是 傳輸延遲（最大）:0.6ns 電源電壓:3 V ~ 3.8 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:Digi-Reel® 產(chǎn)品目錄頁面:1088 (CN2011-ZH PDF) 其它名稱:576-1360-6 |
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