VCCY = 1.65 V to 5.5" />
參數(shù)資料
型號(hào): ADG3308BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 14/20頁
文件大小: 0K
描述: IC XLATOR 8CH 1.2-5.5V 20-TSSOP
標(biāo)準(zhǔn)包裝: 75
邏輯功能: 變換器,雙向
位數(shù): 8
輸入類型: 邏輯
輸出類型: 邏輯
數(shù)據(jù)速率: 50Mbps
通道數(shù): 8
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 6ns
電源電壓: 1.15 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 802 (CN2011-ZH PDF)
Data Sheet
ADG3308/ADG3308-1
Rev. D | Page 3 of 20
SPECIFICATIONS
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. 1
Table 1.
Parameter
Symbol Conditions
Min
Typ2 Max
Unit
LOGIC INPUTS/OUTPUTS
A Side
Input High Voltage3
VIHA
VCCA = 1.15 V
VCCA 0.3
V
VIHA
VCCA = 1.2 V to 5.5 V
0.65 × VCCA
V
Input Low Voltage3
VILA
0.35 × VCCA V
Output High Voltage
VOHA
VY = VCCY, IOH = 20 A, see Figure 29
VCCA 0.4
V
Output Low Voltage
VOLA
VY = 0 V, IOL = 20 A, see Figure 29
0.4
V
Capacitance3
CA
f = 1 MHz, EN = 0, see Figure 34
10
pF
Leakage Current
ILA, HIGH-Z
VA = 0 V or VCCA, EN = 0, see Figure 31
±1
A
Y Side
Input High Voltage3
VIHY
0.65 × VCCY
V
Input Low Voltage3
VILY
0.35 × VCCY
V
Output High Voltage
VOHY
VA = VCCA, IOH = 20 A, see Figure 30
VCCY 0.4
V
Output Low Voltage
VOLY
VA = 0 V, IOL = 20 A, see Figure 30
0.4
V
Capacitance3
CY
f = 1 MHz, EN = 0, see Figure 35
6.8
pF
Leakage Current
ILY, HIGH-Z
VY = 0 V or VCCY, EN = 0, see Figure 32
±1
A
Enable (EN)
Input High Voltage3
VIHEN
ADG3308 (TSSOP, LFCSP)
0.65 × VCCY
V
VCCA = 1.15 V
VCCA 0.3
V
VCCA = 1.2 V to 5.5 V
0.65 × VCCA
V
Input Low Voltage3
VILEN
ADG3308 (TSSOP, LFCSP)
0.35 × VCCY
V
0.35 × VCCA V
Leakage Current
ILEN
VEN = 0 V or VCCY, VA = 0 V, see Figure 33
±1
A
Capacitance3
CEN
4.5
pF
Enable Time3
tEN
RS = RT = 50 , VA = 0 V or
VCCA (A
→Y), VY = 0 V or VCCY (Y→A),
1
1.8
s
SWITCHING CHARACTERISTICS3
3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V
A
→Y Level Translation
RS = RT = 50 , CL = 50 pF, see Figure 37
Propagation Delay
tP, A→Y
6
10
ns
Rise Time
tR, A→Y
2
3.5
ns
Fall Time
tF, A→Y
2
3.5
ns
Maximum Data Rate
DMAX, A→Y
50
Mbps
Channel-to-Channel Skew
tSKEW, A→Y
2
4
ns
Part-to-Part Skew
tPPSKEW,A→Y
3
ns
Y
→A Level Translation
RS = RT = 50 , CL = 15 pF, see Figure 38
Propagation Delay
tP,Y→A
4
7
ns
Rise Time
tR,Y→A
1
3
ns
Fall Time
tF, Y→A
3
7
ns
Maximum Data Rate
DMAX,Y→A
50
Mbps
Channel-to-Channel Skew
tSKEW,Y→A
2
3.5
ns
Part-to-Part Skew
tPPSKEW,Y→A
2
ns
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