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參數(shù)資料
| 型號： | ADM1033ARQ-REEL |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2Cel, RECTANGULAR, SURFACE MOUNT |
| 封裝： | MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 28/39頁 |
| 文件大?。?/td> | 819K |
| 代理商： | ADM1033ARQ-REEL |
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ADM1033
Rev. 0 | Page 34 of 40
Table 42. Register 0x07, Fan BHVR Register, Power-On Default = 0x09, Lock = Y, SW Reset = Y
Bit
Name
R/W
Description
7
Reserved
R
Reserved.
6
Fan Off
R/W
When this bit is set to 1, the fan switches off, regardless of programmed target
fan speed. Default = 0.
<5:2>
Reserved
R
Reserved.
<1:0>
DRIVE BHVR
R/W
Determine which temperature source controls the DRIVE Output.
00 = local temp controls the DRIVE. 01 = remote temperature controls the
DRIVE. 10 = remote temperature controls the DRIVE. 11 = DRIVE at full speed.
Table 43. Register 0x08, Mask Register 1, Power-On Default = 0x52, Lock = N, SW Reset = Y
Bit
Name
R/W
Description
7
Local Temp High
R/W
A 1 disables the corresponding interrupt status bit from causing the interrupt
output to be set. The status bit is not affected. Default = 0.
6
Local Temp Low
R/W
A 1 disables the corresponding interrupt status bit from causing the interrupt
output to be set. The status bit is not affected. Default = 1.
5
Remote High
R/W
A 1 disables the corresponding interrupt status bit from causing the interrupt
output to be set. The status bit is not affected. Default = 0.
4
Remote Low
R
A 1 disables the corresponding interrupt status bit from causing the interrupt
output to be set. The status bit is not affected. Default = 1.
3
Remote Diode Error
R
A 1 disables the corresponding interrupt status bit from causing the interrupt
output to be set. The status bit is not affected. Default = 0.
2
Unused
R
Reserved.
1
Unused
R
Reserved.
0
Unused
R
Reserved.
Table 44. Register 0x09, Mask Register 2, Power-On Default = 0x10, Lock = N, SW Reset = Y
Bit
Name
R/W
Description
<7:5>
Unused
R
Unused.
4
THERM %
R/W
A 1 disables the corresponding interrupt status bit from setting the interrupt
output. The status bit is not affected. Default = 0.
3
THERM Assert
R/W
A 1 disables the corresponding interrupt status bit from setting the interrupt
output. The status bit is not affected. Default = 0.
2
THERM_State
R/W
A 1 disables the corresponding interrupt status bit from setting the interrupt
output. The status bit is not affected. Default = 0. This bit has no effect for the
ALERT Comp output.
<1:0>
Unused
R
Unused.
Table 45. Register 0x0A, Mask Register 3, Power-On Default = 0x00, Lock = N, SW Reset = Y
Bit
Name
R/W
Description
7
Fan Stalled
R/W
A 1 disables the corresponding interrupt status bit from setting the interrupt
output. The status bit is not affected. Default = 0.
6
Fan Alarm Speed
R/W
A 1 disables the corresponding interrupt status bit from setting the interrupt
output. The status bit is not affected. Default = 0.
5
Reserved
R
Reserved. Default = 0.
4
Reserved
R
Reserved. Default = 0.
3
Reserved
R
Reserved. Default = 0.
2
Reserved
R
Reserved. Default = 0.
1
Reserved
R
Reserved. Default = 0.
0
Reserved
R
Reserved. Default = 0.
Rev. 1 | Page 34 of 39 | www.onsemi.com
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