參數(shù)資料
型號(hào)： ADM7008
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Ethernet 10/100M PHY
中文描述： 八路個(gè)10/100M以太網(wǎng)物理層
文件頁(yè)數(shù)： 18/92頁(yè)
文件大小： 981K
代理商： ADM7008
ADM7008
Interface Description
Pin #
Pin Name
Type
Pin Description
CRSDV_P6 is asserted synchronously to REFCLK. The
toggling of CRSDV_P6 on the first and second di-bit continues
until all the data in the FIFO is presented onto RXD.
CRSDV_P6 is asserted for the duration of carrier activity for a
false carrier event.
Not Used.
Not used in SMII/SS_SMII Mode
Port 6 RMII Transmit Data. Transmit data for port 6 input the
di-bits that re transmitted and are driven synchronously to
REFCLK. Note that in 100Mb/s mode, TXD can change once
per REFCLK cycle, whereas in 10Mb/s mode, TXD must be
held steady for 10 consecutive REFCLK cycles.
Link and Activity LED/Port 6 SMII Transmit Data. TXD0 for port
6 inputs the data that is transmitted and is driven synchronously
to SMII_REFCLK (pin 70). In 100Mb/s mode, TXD0 inputs a
new 10-bit segment starting with SYNC. In 10Mb/s mode,
TXD0 must repeat each 10-bit segment 10 times.
TXD1_P6 acts as Port 6 Link/Activity LED in both SMII and
SS_SMII Mode. See LED Description for more detail.
Link and Activity LED/Port 6 SS_SMII Transmit Data. TXD0 for
port 6 inputs the data that is transmitted and is driven
synchronously to TXCLK (pin 70). In 100Mb/s mode, TXD0
inputs a new 10-bit segment starting with SYNC. In 10Mb/s
mode, TXD0 must repeat each 10-bit segment 10 times.
Port 6 Transmit Enable. Transmit Enable for port 6 indicates
that the di-bit on TXD is valid and it is driven synchronously to
REFCLK.
TIED TO LOW. TXEN_P6 should be tied to low for normal
operation in both SMII and SS_SMII Mode.
REC_10M: Value on RXD1_P5 will be latched by ADM7008
during power on reset as Port 5 10M Re-command value.
0: Recommend Port 5 to operate in 100M Mode (Default)
1: Recommend Port 5 to operate in 10M Mode
Lower power Link Pulse Function (Power Saving, LLP) Disable.
Value on RXD1 will be latched by ADM7008 during power on
reset as power saving disable signal. (See Lower Power Link
Pulse Function description for more detail)
0: Power Saving Enable
1: Power Saving disable (Default)
Port 5 RMII Receive Data. RXD[1:0] are the port 5 output di-
bits synchronously to REFCLK. Upon assertion of CRSDV_P,
RXD0 and RXD1 remain at 00 until valid data is output from the
FIFO onto RXD. 01 on RXD1 and RXD0 indicates the start of
valid data. If a false carrier or a symbol error is detected, RXD1
and RXD0 are set to 10 for the duration of the activity. Note
that in 100Mb/s mode RXD can change once per REFCLK
ADMtek Inc.
2-6
SMII/SS_SMII
Mode
N/A
62, 63
RMII Mode
TXD[1:0]_P6
SMII Mode
LNKACT_P6,
SMII_TXD_P6
SS_SMII Mode
LNKACT_P6,
SSSMII_TXD_P6
I,
LVTTL,
PD,
PD
64
RMII Mode
TXEN_P6
SMII/SS_SMII
LOW
Power On
Setting
REC_10M_P5,
PWSAVE_DIS
RMII Mode
RXD[1:0]_P5
I,
TTL
65, 66
I,
PD,
PD
O,
8mA
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