參數(shù)資料
型號(hào)： ADM7008
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Ethernet 10/100M PHY
中文描述： 八路個(gè)10/100M以太網(wǎng)物理層
文件頁數(shù)： 6/92頁
文件大小： 981K
代理商： ADM7008
ADMtek Inc.
V1.0
List of Figures
Figure 1-1 ADM7008 Block Diagram
.......................................................................................1-3
Figure 2-1 ADM7008 Pin Assignment
......................................................................................2-1
Figure 3-1 ADM7008 Switch Application (10/100M TP Mode)
.....................................................3-1
Figure 3-2 100Base-X Block Diagram and Data Path
...................................................................3-3
Figure 3-3 10Base-T Block Diagram and Data Path
...................................................................3-10
Figure 3-4 RMII Signal Diagram
...........................................................................................3-14
Figure 3-5 RMII Reception Without Error
...............................................................................3-15
Figure 3-6 RMII Reception with False Carrier (100M Only)
........................................................3-15
Figure 3-7 RMII Reception with Symbol Error
.........................................................................3-15
Figure 3-8 10M RMII Receive Diagram
..................................................................................3-16
Figure 3-9 100M RMII Transmit Diagram
...............................................................................3-16
Figure 3-10 10M RMII Transmit Diagram
...............................................................................3-17
Figure 3-11 SMII Signal Diagram
..........................................................................................3-18
Figure 3-12 SS_SMII Signal Diagram
.....................................................................................3-18
Figure 3-13 100M SMII Receive Timing Diagram
....................................................................3-18
Figure 3-14 100M SS_SMII Receive Timing Diagram
...............................................................3-18
Figure 3-15 10M SMII Receive Timing Diagram
......................................................................3-19
Figure 3-16 10M SS_SMII Receive Timing Diagram
.................................................................3-19
Figure 3-17 100M SMII Transmit Timing Diagram
...................................................................3-20
Figure 3-18 100M SS_SMII Transmit Timing Diagram
..............................................................3-20
Figure 3-19 10M SMII Transmit Timing Diagram
.....................................................................3-20
Figure 3-20 10M SS_SMII Transmit Timing Diagram
...............................................................3-21
Figure 3-21 Stream LED under RMII Mode
.............................................................................3-24
Figure 3-22 Stream LED under SMII/SS_SMII Mode
................................................................3-24
Figure 3-23 SMI Read Operation
...........................................................................................3-25
Figure 3-24 SMI Write Operation
...........................................................................................3-25
Figure 3-25 Medium Detect Power Management Flow Chart
.......................................................3-27
Figure 3-26 Low Power Link Pulse during TX for Power Management
.........................................3-28
Figure 3-27 External PNP Power Transistor Diagram
.................................................................3-29
Figure 5-1 Crystal/Oscillator Timing
........................................................................................5-2
Figure 5-2 REFCLK Input Timing
...........................................................................................5-3
Figure 5-3 REFCLK Output Timing
.........................................................................................5-4
Figure 5-4 RMII Transmit Timing
............................................................................................5-5
Figure 5-5 RMII Receive Timing
.............................................................................................5-6
Figure 5-6 REFCLK Input Timing
...........................................................................................5-7
Figure 5-7 SMII/SS_SMII REFCLK Output Timing
....................................................................5-8
Figure 5-8 SMII/SS_SMII Transmit Timing
...............................................................................5-9
Figure 5-9 SMII/SS_SMII Receive Timing
..............................................................................5-10
Figure 5-10 Serial Management Interface (MDC/MDIO) Timing
.................................................5-11
Figure 5-11 Power On Configuration Timing
...........................................................................5-12
ADM7008
iv
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