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| 型號： | ADN2850BCPZ250 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL RHEO DL 1024POS 16LFCSP |
| 產(chǎn)品變化通告： | Metal Edit Change 03/Feb/2012 |
| 標準包裝： | 1 |
| 接片： | 1024 |
| 電阻（歐姆）： | 250k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 3 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP |
| 包裝： | 托盤 |
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Data Sheet
ADN2850
Rev. E | Page 5 of 28
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 k, 250 k VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 3 V and VDD = 5 V.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
Clock Cycle Time (tCYC)
t1
20
ns
EE
AA
Setup Time
CS
t2
10
ns
CLK Shutdown Time to
AA
CSEE
AA
Rise
t3
1
tCYC
Input Clock Pulse Width
t4, t5
Clock level high or low
10
ns
Data Setup Time
t6
From positive CLK transition
5
ns
Data Hold Time
t7
From positive CLK transition
5
ns
AA
CSEE
AA
to SDO-SPI Line Acquire
t8
40
ns
AA
CSEE
AA
to SDO-SPI Line Release
t9
50
ns
CLK to SDO Propagation Delay
t10
RP = 2.2 k, CL < 20 pF
50
ns
CLK to SDO Data Hold Time
t11
RP = 2.2 k, CL < 20 pF
0
ns
AA
CSEE
AA
High Pulse Width
t12
10
ns
AA
CS
EE
AA
High to
AA
CSEE
AA
High3
t13
4
tCYC
RDY Rise to
AA
CSEE
AA
Fall
t14
0
ns
AA
CSEE
AA
Rise to RDY Fall Time
t15
0.15
0.3
ms
Store EEMEM Time
t16
Applies to instructions 0x2, 0x3
15
50
ms
Read EEMEM Time4
t16
Applies to instructions 0x8, 0x9, 0x10
7
30
s
AA
CSEE
AA
Rise to Clock Rise/Fall Setup
t17
10
ns
Preset Pulse Width (Asynchronous)
tPRW
50
ns
Preset Response Time to Wiper Setting6
tPRESP
AA
PREE
AA
pulsed low to refresh wiper positions
30
s
Power-On EEMEM Restore Time6
tEEMEM
30
s
FLASH/EE MEMORY RELIABILITY
Endurance
TA = 25°C
1
MCycles
100
kCycles
Data Retention
100
Years
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3
Valid for commands that do not activate the RDY pin.
4
RDY pin low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 s; CMD_9, CMD_10 ~ 7 s;
CMD_2, CMD_3 ~ 15 ms, PR hardware pulse ~ 30 s.
5
Store EEMEM time depends on the temperature and EEMEM write cycles. Higher timing is expected at lower temperature and higher write cycles.
6
Not shown in Figure 2 and Figure 3.
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 40°C, +25°C, and +85°C.
8
Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
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