參數(shù)資料
型號: ADP1871ACPZ-0.3-R7
廠商: ANALOG DEVICES INC
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, PDSO10
封裝: 3 X 3 MM, ROHS COMPLIANT, LFCSP-10
文件頁數(shù): 21/44頁
文件大?。?/td> 1958K
代理商: ADP1871ACPZ-0.3-R7
ADP1870/ADP1871
When the desired valley current limit (I
CLIM
) has been determined,
the current-sense gain can be calculated as follows:
V
4
Rev. A | Page 21 of 44
The valley current limit is programmed as outlined in Table 7
and Figure 71. The inductor chosen must be rated to handle the
peak current, which is equal to the valley current from Table 7
plus the peak-to-peak inductor ripple current (see the Inductor
Selection section). In addition, the peak current value must be
used to compute the worst-case power dissipation in the
MOSFETs (see Figure 72).
ON
CS
CLIM
R
A
I
×
=
where:
R
ON
is the channel impedance of the lower-side MOSFET.
A
CS
is the current-sense gain multiplier (see Table 6 and Table 7).
Although the ADP1870/ADP1871 have only four discrete current-
sense gain settings for a given R
ON
variable, Table 7 and Figure 71
outline several available options for the valley current setpoint
based on various R
ON
values.
INDUCTOR
CURRENT
VALLEY CURRENT-LIMIT
THRESHOLD (SET FOR 25A)
Δ
I = 33%
COMP
OUTPUT
SWING
COMP
OUTPUT
2.4V
1V
0A
35A
30A
32.25A
37A
49A
39.5A
I = 45%
Δ
Δ
I = 65%
MAXIMUM DC LOAD
CURRENT
0
Table 7. Valley Current Limit Program
1
R
ON
(mΩ)
1.5
2
2.5
3
3.5
4.5
5
5.5
10
15
18
1
Refer to Figure 71 for more information and a graphical representation.
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
Valley Current Level
22 kΩ
A
CS
= 6 V/V
23.3
15.5
13.0
47 kΩ
A
CS
= 3 V/V
31.0
26.0
Open
A
CS
= 12 V/V
39.0
33.4
26.0
23.4
21.25
11.7
7.75
6.5
100 kΩ
A
CS
= 24 V/V
38.9
29.2
23.3
19.5
16.7
13
11.7
10.6
5.83
7.5
3.25
Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current
HICCUP MODE DURING SHORT CIRCUIT
A current-limit violation occurs when the current across the
source and drain of the lower-side MOSFET exceeds the
current-limit setpoint. When 32 current-limit violations are
detected, the controller enters idle mode and turns off the
MOSFETs for 6 ms, allowing the converter to cool down. Then,
the controller reestablishes soft start and begins to cause the
output to ramp up again (see Figure 73). While the output
ramps up, COMP is monitored to determine if the violation is
still present. If it is still present, the idle event occurs again,
followed by the full-chip power-down sequence. This cycle
continues until the violation no longer exists. If the violation
disappears, the converter is allowed to switch normally,
maintaining regulation.
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
R
ON
(m
)
V
RES = 47k
A
CS
= 3V/V
RES = 22k
A
CS
= 6V/V
RES = NO RES
A
CS
= 12V/V
RES = 100k
A
CS
= 24V/V
0
Figure 71. Valley Current-Limit Value vs. R
ON
of the Lower-Side MOSFET
for Each Programming Resistor (RES)
HS
CLIM
ZERO
CURRENT
REPEATED CURRENT-LIMIT
VIOLATION DETECTED
A PREDETERMINED NUMBER
OF PULSES IS COUNTED TO
ALLOW THE CONVERTER
TO COOL DOWN
SOFT START IS
REINITIALIZED TO
MONITOR IF THE
VIOLATION
STILL EXISTS
0
Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation
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