參數(shù)資料
型號(hào)： ADP1871ACPZ-0.3-R7
廠商： ANALOG DEVICES INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, PDSO10
封裝： 3 X 3 MM, ROHS COMPLIANT, LFCSP-10
文件頁(yè)數(shù)： 6/44頁(yè)
文件大?。?/td> 1958K
代理商： ADP1871ACPZ-0.3-R7
ADP1870/ADP1871
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. A | Page 6 of 44
VIN
1
COMP/EN
2
FB
3
GND
4
VREG
5
BST
10
SW
9
DRVH
8
PGND
7
DRVL
6
ADP1870/
ADP1871
TOP VIEW
(Not to Scale)
0
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO GROUND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1
VIN
2
COMP/EN
3
FB
4
GND
Description
High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground
plane (see the Layout Considerations section).
Internal Regulator Supply Bias Voltage for the ADP1870/ADP1871 Controller (Includes the Output Gate Drivers).
A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VREG and GND are recommended.
VREG should not be loaded externally because it is intended to only bias internal circuitry.
Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain
setting pin (see Figure 69).
Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET.
Drive Output for the External Upper-Side, N-Channel MOSFET.
Switch Node Connection.
Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be
connected between VREG and BST for increased gate drive capability.
5
VREG
6
DRVL
7
8
9
10
PGND
DRVH
SW
BST
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