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參數(shù)資料
| 型號： | ADSP-2101BPZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP SLG 16BIT 25MHZ 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 同步串行端口（SSP） |
| 時鐘速率： | 25MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 6kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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ADSP-21xx
–28–
REV. B
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
t
DECAY =
C
L × 0.5 V
i
L
from which
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t ENA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 27. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
SPECIFICATIONS (ADSP-2103/2162/2164)
TEST CONDITIONS
Figure 26 shows voltage reference levels for ac measurements.
Figure 26. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 27. The time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
INPUT
OUTPUT
VDD
2
VDD
2
2.0V
1.0V
t
ENA
REFERENCE
SIGNAL
OUTPUT
t
DECAY
VOH (MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
t
DIS
t
MEASURED
VOL (MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
VOH (MEASURED)
VOL (MEASURED)
TO
OUTPUT
PIN
50pF
IOH
IOL
VDD
2
Figure 27. Output Enable/Disable
Figure 28. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)
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