Timing Requirement: t
參數(shù)資料
型號: ADSP-2101BPZ-100
廠商: Analog Devices Inc
文件頁數(shù): 40/64頁
文件大?。?/td> 0K
描述: IC DSP SLG 16BIT 25MHZ 68-PLCC
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 同步串行端口(SSP)
時鐘速率: 25MHz
非易失內(nèi)存: 外部
芯片上RAM: 6kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
包裝: 管件
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
ADSP-21xx
REV. B
–45–
Frequency
10.24 MHz
Dependency
Parameter
Min
Max
Min
Max
Unit
Timing Requirement:
tCK
CLKIN Period
97.6
150
ns
tCKL
CLKIN Width Low
20
ns
tCKH
CLKIN Width High
20
ns
tRSP
RESET Width Low
488
5tCK
1
ns
Switching Characteristic:
tCPL
CLKOUT Width Low
38.8
0.5tCK – 10
ns
tCPH
CLKOUT Width High
38.8
0.5tCK – 10
ns
tCKOH
CLKIN High to CLKOUT High
0
20
ns
NOTES
1Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator startup time).
TIMING PARAMETERS (ADSP-2103/2162/2164)
CLOCK SIGNALS & RESET
Figure 39. Clock Signals
CLKIN
CLKOUT
t
CKH
t
CK
t
CKL
t
CKOH
t
CPH
t
CPL
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