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參數(shù)資料
| 型號： | ADSP-21065LCCAZ240 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CTLR 32BIT 196CSPBGA |
| 產(chǎn)品培訓模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 60MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-BGA，CSPBGA |
| 供應商設備封裝： | 196-CSPBGA（15x15） |
| 包裝： | 托盤 |
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REV. C
ADSP-21065L
–11–
The BTMS, BTCK,
BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If you are not
going to use the test access port for board testing, tie
BTRST
to GND and tie or pull-up BTCK to VDD. The TRST pin must
be asserted after power-up (through
BTRST on the connector)
or held low for proper operation of the ADSP-2106x. None of
the Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal
Termination
TMS
Driven through 22
W resistor (16 mA driver)
TCK
Driven at 10 MHz through 22
W resistor
(16 mA driver)
TRST*
Driven through 22
W resistor (16 mA driver)
(pulled up by on-chip 20 k
W resistor)
TDI
Driven by 22
W resistor (16 mA driver)
TDO
One TTL load, Split Termination (160/220)
CLKIN
One TTL load, Split Termination (160/220).
(Caution: Do not connect to CLKIN if
internal XTAL oscillator is used.)
EMU
Active Low 4.7 k
W pull-up resistor, one TTL
load (open-drain output from ADSP-2106xs)
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up,
TRST is driven high.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform
operations such as starting, stopping, and single-stepping two
ADSP-21065Ls in a synchronous manner. If you do not need
these operations to occur synchronously on the two processors,
simply tie Pin 4 of the EZ-ICE header to ground.
For systems which use the internal clock generator and an external
discrete crystal, do not directly connect the CLKIN pin to the
JTAG probe. This will load the oscillator circuit and possibly
cause it to fail to oscillate. Instead the JTAG probe’s CLKIN
can be driven by the XTAL pin through a high impedance buffer.
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between multiple ADSP-2106x
processors and the CLKIN pin on the EZ-ICE header must be
minimal. If the skew is too large, synchronous operations may
be off by one cycle between processors. For synchronous multi-
processor operation TCK, TMS, CLKIN and
EMU should be
treated as critical signals in terms of skew, and should be laid
out as short as possible on your board.
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO,
EMU and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family
JTAG EZ-ICE User’s Guide and Reference.
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| ADSP-21065LKCA-264 | 功能描述:IC DSP CTLR 32BIT 196CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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