參數(shù)資料
型號(hào)： ADSP-21065LCCAZ240
廠商： Analog Devices Inc
文件頁數(shù)： 44/44頁
文件大小： 0K
描述： IC DSP CTLR 32BIT 196CSPBGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 60MHz
非易失內(nèi)存： 外部
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 196-CSPBGA（15x15）
包裝： 托盤
REV. C
ADSP-21065L
–9–
Pin
Type
Function
BMS
I/O/T
*
Boot Memory Select. Output: used as chip select for boot EPROM devices (when BSEL = 1).
In a multiprocessor system,
BMS is output by the bus master. Input: When low, indicates that
no booting will occur and that the ADSP-21065L will begin executing instructions from exter-
nal memory. See following table. This input is a system configuration selection which should be
hardwired.
*Three-statable only in EPROM boot mode (when BMS is an output).
BSEL
BMS
Booting Mode
1Output
EPROM (connect
BMS to EPROM chip select).
01 (Input)
Host processor (HBW [SYSCON] bit selects host bus width).
00 (Input)
No booting. Processor executes from external memory.
CLKIN
I
Clock In. Used in conjunction with XTAL, configures the ADSP-21065L to use either its
internal clock generator or an external clock source. The external crystal should be rated at 1x
frequency.
Connecting the necessary components to CLKIN and XTAL enables the internal clock genera-
tor. The ADSP-21065L’s internal clock generator multiplies the 1x clock to generate 2x clock
for its core and SDRAM. It drives 2x clock out on the SDCLKx pins for the SDRAM interface
to use. See also SDCLKx.
Connecting the 1x external clock to CLKIN while leaving XTAL unconnected configures the
ADSP-21065L to use the external clock source. The instruction cycle rate is equal to 2x CLKIN.
CLKIN may not be halted, changed, or operated below the specified frequency.
RESET
I/A
Processor Reset. Resets the ADSP-21065L to a known state and begins execution at the
program memory location specified by the hardware reset vector address. This input must be
asserted at power-up.
TCK
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k
W internal
pull-up resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k
W
internal pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG). Resets the test state machine.
TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-21065L.
TRST has a 20 k
W internal
pull-up resistor.
EMU (O/D)
O
Emulation Status. Must be connected to the ADSP-21065L EZ-ICE target board connector
only.
BMSTR
O
Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21065L is cur-
rent bus master of the shared external bus. The ADSP-21065L drives BMSTR high only while
it is the bus master. In a single-processor system (ID = 00), the processor drives this pin high.
CAS
I/O/T
SDRAM Column Access Strobe. Provides the column address. In conjunction with
RAS,
MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
RAS
I/O/T
SDRAM Row Access Strobe. Provides the row address. In conjunction with
CAS, MSx,
SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
SDWE
I/O/T
SDRAM Write Enable. In conjunction with
CAS, RAS, MSx, SDCLKx, and sometimes
SDA10, defines the operation for the SDRAM to perform.
DQM
O/T
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used to block write
operations.
SDCLK1-0
I/O/S/T
SDRAM 2x Clock Output. In systems with multiple SDRAM devices connected in parallel,
supports the corresponding increased clock load requirements, eliminating need of off-chip
clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.
SDCKE
I/O/T
SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet
supplied with your SDRAM device.
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