Capacitive Loading Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 29). F" />
參數(shù)資料
型號(hào): ADSP-21160NKB-100
廠商: Analog Devices Inc
文件頁(yè)數(shù): 37/48頁(yè)
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 400BGA
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: 主機(jī)接口,連接端口,串行端口
時(shí)鐘速率: 100MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.90V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 400-BBGA
供應(yīng)商設(shè)備封裝: 400-PBGA(27x27)
包裝: 托盤
ADSP-21160N
–42–
REV. 0
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 29). Figure 31 and Figure 32 show
how output rise time varies with capacitance. Figure 33 graphi-
cally shows how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see Output Disable Time on Page 41.)
The graphs of Figure 31, Figure 32, and Figure 33 may not be
linear outside the ranges shown.
Environmental Conditions
The ADSP-21160NKB-100 and ADSP-21160NCB-100 are
provided in a 400-Ball Metric PBGA (Plastic Ball Grid Array)
package.
Thermal Characteristics
The ADSP-21160N is specified for a case temperature (TCASE).
To ensure that the TCASE data sheet specification is not exceeded,
a heatsink and/or an air flow source may be used. Use the cen-
terblock of ground pins (PBGA balls: F7-14, G7-14, H7-14,
J7-14, K7-14, L7-14, M-14, N7-14, P7-14, R7-15) to provide
thermal pathways to the printed circuit board’s ground plane. A
heatsink should be attached to the ground plane (as close as
possible to the thermal pathways) with a thermal adhesive.
T
CASE = Case temperature (measured on top surface
of package)
PD = Power dissipation in W (this value depends upon
the specific application; a method for calculating PD is
shown under Power Dissipation).
θ
CA = Value from Table 31.
θ
JB = 6.46°C/W
Figure 31. Typical Output Rise Time (20%–80%,
VDDEXT = Max) vs. Load Capacitance
Figure 32. Typical Output Rise Time (20%–80%,
VDDEXT = Min) vs. Load Capacitance
LOAD CAPACITANCE – pF
0
250
50
100
150
200
TBD
R
IS
E
A
N
D
F
A
L
T
IM
E
S
n
s
RISE TIME
FALL TIME
Y = 0.0751x +1.4882
Y = 0.0716x + 2.9043
2
4
6
8
10
12
14
16
18
20
LOAD CAPACITANCE – pF
20
0
250
50
100
150
200
10
5
25
15
TBD
R
IS
E
A
N
D
F
A
L
T
IM
E
S
n
s
FALL TIME
Y = 0.0834x +1.0653
Y = 0.0813x +2.312
RISE TIME
Figure 33. Typical Output Delay or Hold vs. Load
Capacitance (at Max Case Temperature)
Table 31. Airflow Over Package Versus
θ
CA
Airflow (Linear Ft./Min.)
0
200
400
θ
CA (°C/W)
1
θ
JC = 3.6 °C/W.
12.13
9.86
8.7
LOAD CAPACITANCE – pF
4
–2
0250
50
100
150
200
0
–4
6
2
O
U
T
P
U
T
D
E
L
A
Y
O
R
H
O
L
D
n
s
Y = 0.0716x – 3.9037
8
10
12
T
CASE
T
AMB
PD
θ
CA
×
()
+
=
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