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參數(shù)資料
| 型號： | ADSP-21160NKB-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 45/48頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400BGA |
| 產品培訓模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，連接端口，串行端口 |
| 時鐘速率： | 100MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.90V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應商設備封裝： | 400-PBGA（27x27） |
| 包裝： | 托盤 |
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ADSP-21160N
–6–
REV. 0
PM data, DM addresses, DM data, I/O addresses, and I/O data—
are multiplexed at the external port to create an external system
bus with a single 32-bit address bus and a single 64-bit data bus.
The lower 32 bits of the external data bus connect to even
addresses and the upper 32 bits of the 64 connect to odd
addresses. Every access to external memory is based on an
address that fetches a 32-bit word, and with the 64-bit bus, two
address locations can be accessed at once. When fetching an
instruction from external memory, two 32-bit data locations are
being accessed (16 bits are unused). Figure 3 shows the
alignment of various accesses to external memory.
The external port supports asynchronous, synchronous, and syn-
chronous burst accesses. ZBT synchronous burst SRAM can be
interfaced gluelessly. Addressing of external memory devices is
facilitated by on-chip decoding of high order address lines to
generate memory bank select signals. Separate control lines are
also generated for simplified addressing of page-mode DRAM.
The ADSP-21160N provides programmable memory wait states
and external memory acknowledge controls to allow interfacing
to DRAM and peripherals with variable access, hold, and disable
time requirements.
DMA Controller
The ADSP-21160N’s on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions. DMA
transfers can occur between the ADSP-21160N’s internal
memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP-
21160N’s internal memory and its serial ports or link ports.
External bus packing to 16-, 32-, 48-, or 64-bit words is
performed during DMA transfers. Fourteen channels of DMA
are available on the ADSP-21160N—six via the link ports, four
via the serial ports, and four via the processor’s external port (for
either host processor, other ADSP-21160Ns, memory or I/O
transfers). Programs can be downloaded to the ADSP-21160N
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(
DMAR1–2, DMAG1–2). Other DMA features include
interrupt generation upon completion of DMA transfers, two-
dimensional DMA, and DMA chaining for automatic linked
DMA transfers.
Multiprocessing
The ADSP-21160N offers powerful features tailored to multi-
processing DSP systems as shown in Figure 4. The external port
and link ports provide integrated glueless multiprocessing
support.
The external port supports a unified address space (see Figure 2)
that allows direct interprocessor accesses of each ADSP-
21160N’s internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems con-
taining up to six ADSP-21160Ns and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus
lock allows indivisible read-modify-write sequences for sema-
phores. A vector interrupt is provided for interprocessor
Figure 2. Memory Map
0x00 0000
0x02 0000
0x04 0000
0x08 0000
0x10 0000
0x20 0000
0x30 0000
0x40 0000
0x50 0000
0x60 0000
0x70 0000
0x7F FFFF
0x80 0000
0xFFFF FFFF
Internal
Memory
Space
External
Memory
Space
IOP Reg’s
Long Word
Normal Word
Short Word
Internal
Space
Internal
Space
Internal
Space
Internal
Space
Internal
Space
Internal
Space
Broadcast
All DSPs
Bank 0
Bank 1
Bank 2
Bank 3
Nonbanked
MS0
MS1
MS2
MS3
Memory
(ID = 011)
(ID = 100)
Memory
(ID = 101)
Memory
(ID = 110)
Write to
(ID = 111)
Memory
(ID = 010)
Memory
(ID = 001)
Multiprocessor
Memory
Space
Figure 3. External Data Alignment Options
DATA63–0
63
55
47
39
31
23
15
7
0
RDH/WRH
RDL/WRL
EPROM
16-BIT PACKED
32-BIT PACKED
64-BIT TRANSFER FOR 40-BIT EXTENDED PRECISION
64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH
RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:
64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS
BYTE 0
BYTE 7
32-BIT NORMAL WORD (EVEN ADDRESS)
32-BIT NORMAL WORD (ODD ADDRESS)
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| ADSP-21160NKB-95 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NKB-X | 制造商:Analog Devices 功能描述: |
| ADSP-21160NKBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161N | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21161NCCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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