參數(shù)資料
型號(hào)： ADSP-21369KSWZ-2A
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 62/64頁(yè)
文件大?。?/td> 0K
描述： IC DSP 32BIT 233MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI
時(shí)鐘速率： 333MHz
非易失內(nèi)存： ROM（768 kB）
芯片上RAM： 256kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 208-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 208-LQFP-EP（28x28）
包裝： 托盤(pán)
配用： ADZS-21369-EZLITE-ND - KIT EVAL EZ LITE ADDS-21369
Rev. F
|
Page 7 of 64
|
October 2013
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-21367/ADSP-21368/ADSP-21369 family contains a
rich set of peripherals that support a wide variety of applications
including high quality audio, medical imaging, communica-
tions, military, test equipment, 3D graphics, speech recognition,
motor control, imaging, and other applications.
External Port
The external port interface supports access to the external mem-
ory through core and DMA accesses. The external memory
address space is divided into four banks. Any bank can be pro-
grammed as either asynchronous or synchronous memory. The
external ports of the ADSP-21367/8/9 processors are comprised
of the following modules.
An Asynchronous Memory Interface which communicates
with SRAM, FLASH, and other devices that meet the stan-
dard asynchronous SRAM access protocol. The AMI
supports 14M words of external memory in bank 0 and
16M words of external memory in bank 1, bank 2, and
bank 3.
An SDRAM controller that supports a glueless interface
with any of the standard SDRAMs. The SDC supports 62M
words of external memory in bank 0, and 64M words of
external memory in bank 1, bank 2, and bank 3.
Arbitration Logic to coordinate core and DMA transfers
between internal and external memory over the external
port.
A Shared Memory Interface that allows the connection of
up to four ADSP-21368 processors to create shared exter-
nal bus systems (ADSP-21368 only).
SDRAM Controller
The SDRAM controller provides an interface of up to four sepa-
rate banks of industry-standard SDRAM devices or DIMMs, at
speeds up to f
SCLK. Fully compliant with the SDRAM standard,
each bank has its own memory select line (MS0–MS3), and can
be configured to contain between 16M bytes and 128M bytes of
memory. SDRAM external memory address space is shown in
A set of programmable timing parameters is available to config-
ure the SDRAM banks to support slower memory devices. The
memory banks can be configured as either 32 bits wide for max-
imum performance and bandwidth or 16 bits wide for
minimum device count and lower system cost.
The SDRAM controller address, data, clock, and control pins
can drive loads up to distributed 30 pF loads. For larger memory
systems, the SDRAM controller external buffer timing should
be selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
External Memory
The external port provides a high performance, glueless inter-
face to a wide variety of industry-standard memory devices. The
32-bit wide bus can be used to interface to synchronous and/or
asynchronous memory devices through the use of its separate
internal memory controllers. The first is an SDRAM controller
for connection of industry-standard synchronous DRAM
devices and DIMMs (dual inline memory module), while the
second is an asynchronous memory controller intended to
interface to a variety of memory devices. Four memory select
pins enable up to four separate devices to coexist, supporting
any desired combination of synchronous and asynchronous
device types. Non-SDRAM external memory address space is
shown in Table 5.
Shared External Memory
The ADSP-21368 processor supports connecting to common
shared external memory with other ADSP-21368 processors to
create shared external bus processor systems. This support
includes:
Distributed, on-chip arbitration for the shared external bus
Fixed and rotating priority bus arbitration
Bus time-out logic
Bus lock
Multiple processors can share the external bus with no addi-
tional arbitration logic. Arbitration logic is included on-chip to
allow the connection of up to four processors.
Bus arbitration is accomplished through the BR1–4 signals and
the priority scheme for bus arbitration is determined by the set-
ting of the RPBA pin. Table 8 on Page 13 provides descriptions
of the pins used in multiprocessor systems.
External Port Throughput
The throughput for the external port, based on 166 MHz clock
and 32-bit data bus, is 221M bytes/s for the AMI and 664M
bytes/s for SDRAM.
Table 4. External Memory for SDRAM Addresses
Bank
Size in
Words
Address Range
Bank 0
62M
0x0020 0000–0x03FF FFFF
Bank 1
64M
0x0400 0000–0x07FF FFFF
Bank 2
64M
0x0800 0000–0x0BFF FFFF
Bank 3
64M
0x0C00 0000–0x0FFF FFFF
Table 5. External Memory for Non-SDRAM Addresses
Bank
Size in
Words
Address Range
Bank 0
14M
0x0020 0000–0x00FF FFFF
Bank 1
16M
0x0400 0000–0x04FF FFFF
Bank 2
16M
0x0800 0000–0x08FF FFFF
Bank 3
16M
0x0C00 0000–0x0CFF FFFF
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