參數(shù)資料
型號: ADSP-21489KSWZ-3B
廠商: Analog Devices Inc
文件頁數(shù): 21/68頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROCESSOR 176LQFP
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: EBI/EMI,DAI,I²C,SPI,SPORT,UART/USART
時鐘速率: 350MHz
非易失內(nèi)存: 外部
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.10V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 176-LQFP-EP(24x24)
包裝: 托盤
Rev. B
|
Page 28 of 68
|
March 2013
Timer PWM_OUT Cycle Timing
The following timing specification applies to timer0 and timer1
in PWM_OUT (pulse-width modulation) mode. Timer signals
are routed to the DPI_P14–1 pins through the DPI SRU. There-
fore, the timing specifications provided below are valid at the
DPI_P14–1 pins.
Timer WDTH_CAP Timing
The following timing specification applies to timer0 and timer1,
and in WDTH_CAP (pulse-width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the timing specification provided below is valid
at the DPI_P14–1 pins.
Table 25. Timer PWM_OUT Timing
Parameter
Min
Max
Unit
Switching Characteristic
tPWMO
Timer Pulse Width Output
2 × tPCLK – 1.2
2 × (231 – 1) × tPCLK
ns
Figure 12. Timer PWM_OUT Timing
PWM
OUTPUTS
tPWMO
Table 26. Timer Width Capture Timing
Parameter
Min
Max
Unit
Timing Requirement
tPWI
Timer Pulse Width
2 × tPCLK
2 × (231 – 1) × tPCLK
ns
Figure 13. Timer Width Capture Timing
TIMER
CAPTURE
INPUTS
tPWI
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