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參數(shù)資料
| 型號： | ADSP-21489KSWZ-3B |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 51/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 176LQFP |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | EBI/EMI，DAI，I²C，SPI，SPORT，UART/USART |
| 時鐘速率： | 350MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP 裸露焊盤 |
| 供應商設備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤 |
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Rev. B
|
Page 55 of 68
|
March 2013
OUTPUT DRIVE CURRENTS
Figure 41 shows typical I-V characteristics for the output driv-
ers of the ADSP-2148x, and Table 55 shows the pins associated
with each driver. The curves represent the current drive capabil-
ity of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 21 on Page 26 through Table 54 on Page 54. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 42.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 43. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
graphically how output delays and holds vary with load capaci-
linear outside the ranges shown for Typical Output Delay vs.
Load Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
Table 55. Driver Types
Driver Type Associated Pins
A
FLAG[0–3], AMI_ADDR[0–23], DATA[0–15],
AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,
SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU, TDO,
RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO,
MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK
BSDCLK
Figure 41. Typical Drive at Junction Temperature
Figure 43. Voltage Reference Levels for AC Measurements
SWEEP (V
DDEXT) VOLTAGE (V)
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
0
100
200
SOURCE/SINK
(V
DDEXT
)CURRENT
(mA)
150
50
-100
-200
-150
-50
V
OH 3.13 V, 125 °C
V
OL 3.13 V, 125 °C
TYPE A
TYPE B
INPUT
OR
OUTPUT
1.5V
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 44. Typical Output Rise/Fall Time
(20% to 80%, VDD_EXT = Max)
T1
ZO = 50
(impedance)
TD = 4.04
r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
0.5pF
70
400
45
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
LOAD CAPACITANCE (pF)
6
0
7
4
2
1
3
RISE
AND
FALL
TIMES
(ns)
125
200
100
25
175
50
75
150
5
y = 0.0341x + 0.3093
y = 0.0153x + 0.2131
y = 0.0414x + 0.2661
y = 0.0152x + 0.1882
TYPE A DRIVE FALL
TYPE A DRIVE RISE
TYPE B DRIVE FALL
TYPE B DRIVE RISE
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