External Port Write Cycle Timing Table 12 and Figure 11 describe external port write operations. The external port lets " />
參數(shù)資料
型號: ADSP-2191MKCAZ-160
廠商: Analog Devices Inc
文件頁數(shù): 15/48頁
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 144MBGA
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 主機(jī)接口,SPI,SSP,UART
時鐘速率: 160MHz
非易失內(nèi)存: 外部
芯片上RAM: 160kB
電壓 - 輸入/輸出: 3.00V,3.30V
電壓 - 核心: 2.50V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-迷你型BGA
包裝: 托盤
ADSP-2191M
–22–
REV. A
External Port Write Cycle Timing
Table 12 and Figure 11 describe external port write operations.
The external port lets systems extend read/write accesses in three
ways: waitstates, ACK input, and combined waitstates and ACK.
To add waits with ACK, the DSP must see ACK low at the rising
edge of EMI clock. ACK low causes the DSP to wait, and the
DSP requires two EMI clock cycles after ACK goes high to finish
the access. For more information, see the External Port chapter
in the ADSP-219x/ADSP-2191 DSP Hardware Reference.
Table 12. External Port Write Cycle Timing
Parameter1, 2
Min
Max
Unit
Switching Characteristics
t
CSWS
Chip Select Asserted to
WR Asserted Delay
0.5t
HCLK –4
ns
t
AWS
Address Valid to
WR Setup and Delay
0.5t
HCLK –3
ns
t
WSCS
WR Deasserted to Chip Select Deasserted
0.5t
HCLK –4
ns
t
WSA
WR Deasserted to Address Invalid
0.5t
HCLK –3
ns
t
WW
WR Strobe Pulsewidth
t
HCLK –2+ W
3
ns
t
CDA
WR to Data Enable Access Delay
0ns
t
CDD
WR to Data Disable Access Delay
0.5t
HCLK – 3
0.5t
HCLK +4
ns
t
DSW
Data Valid to
WR Deasserted Setup
t
HCLK +1+W
3
t
HCLK +7+W
3
ns
t
DHW
WR Deasserted to Data Invalid Hold Time; E_WHC4
3.4
ns
t
DHW
WR Deasserted to Data Invalid Hold Time; E_WHC4
t
HCLK +3.4
ns
t
WWR
WR Deasserted to WR, RD Asserted
t
HCLK
Timing Requirements
t
AKW
ACK Strobe Pulsewidth
12.5
ns
t
DWSAK
ACK Delay from
WR Low
0
ns
1t
HCLK is the peripheral clock period.
2These are timing parameters that are based on worst-case operating conditions.
3W = (number of waitstates specified in wait register)
tHCLK.
4Write hold cycle–memory select control registers (MS
CTL).
Figure 11. External Port Write Cycle Timing
D 15–0
tAW S
tWW
tAKW
tDH W
tCD D
AC K
WR
A 21–0
M S 3–0
IO M S
BM S
tCSW S
tWS A
tWS C S
tCD A
tDW SA K
RD
tDS W
tWW R
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