External Port Read Cycle Timing Table 13 and Figure 12 describe external port read operations. For additional informatio" />
參數資料
型號: ADSP-2191MKCAZ-160
廠商: Analog Devices Inc
文件頁數: 16/48頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 144MBGA
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,SPI,SSP,UART
時鐘速率: 160MHz
非易失內存: 外部
芯片上RAM: 160kB
電壓 - 輸入/輸出: 3.00V,3.30V
電壓 - 核心: 2.50V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應商設備封裝: 144-迷你型BGA
包裝: 托盤
–23–
REV. A
ADSP-2191M
External Port Read Cycle Timing
Table 13 and Figure 12 describe external port read operations.
For additional information on the ACK signal, see the discussion
Table 13. External Port Read Cycle Timing
Parameter1, 2
Min
Max
Unit
Switching Characteristics
t
CSRS
Chip Select Asserted to
RD Asserted Delay
0.5t
HCLK –3
ns
t
ARS
Address Valid to
RD Setup and Delay
0.5t
HCLK –3
ns
t
RSCS
RD Deasserted to Chip Select Deasserted Setup
0.5t
HCLK –2
ns
t
RW
RD Strobe Pulsewidth
t
HCLK –2+ W
3
ns
t
RSA
RD Deasserted to Address Invalid Setup
0.5t
HCLK –2
ns
t
RWR
RD Deasserted to WR, RD Asserted
t
HCLK
Timing Requirements
t
AKW
ACK Strobe Pulsewidth
t
HCLK
ns
t
RDA
RD Asserted to Data Access Setup
t
HCLK –4 +W
3
ns
t
ADA
Address Valid to Data Access Setup
t
HCLK +W
3
ns
t
SDA
Chip Select Asserted to Data Access Setup
t
HCLK +W
3
ns
t
SD
Data Valid to
RD Deasserted Setup
7
ns
t
HRD
RD Deasserted to Data Invalid Hold
0
ns
t
DRSAK
ACK Delay from
RD Low
0
ns
1t
HCLK is the peripheral clock period.
2These are timing parameters that are based on worst-case operating conditions.
3W = (number of waitstates specified in wait register)
tHCLK.
Figure 12. External Port Read Cycle Timing
D15–0
tARS
tRW
tAKW
tCDA
tRDA
tADA
tSDA
tSD
tHRD
ACK
RD
A21–0
tCSRS
tRSA
tRSCS
tDRSAK
tRWR
MS3--0
IOMS
BMS
WR
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