參數(shù)資料
型號(hào): ADSP-21991
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述: SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個(gè)DAC
文件頁(yè)數(shù): 36/44頁(yè)
文件大?。?/td> 589K
代理商: ADSP-21991
ADSP-21991
–36–
REV. 0
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t
ENA
is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (
Figure 18
). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation at
Output Disable Time
on Page 35
. Choose
V to be the difference between the output
voltage of the ADSP-21991 and the input threshold for the device
requiring the hold time. A typical
V will be 0.4 V. C
L
is the total
bus capacitance (per data line), and I
L
is the total leakage or three-
state current (per data line). The hold time will be t
DECAY
plus the
minimum disable time (i.e., t
DATRWH
for the write cycle).
Pin Configurations
Table 16
identifies the signal for each Mini-BGA ball number.
Table 17
identifies the Mini-BGA ball number for each signal
name.
Table 18
identifies the signal for each LQFP lead.
Table 19
identifies the LQFP lead for each signal name.
Table 4
describes each signal.
Figure 19. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 20. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
INPUT
OR
OUTPUT
1.5V
1.5V
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