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| 型號： | ADSP-BF512BSWZ-4 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/68頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16/32B 400MHZ LP 176LQFP |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | I²C，PPI，SPI，SPORT，UART/USART |
| 時(shí)鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 116kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤 |
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Rev. B
|
Page 12 of 68
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January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wakeup causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the proces-
sor to transition to the Active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the full
on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and system
blocks (SCLK). Any critical information stored internally (for
example memory contents, register contents) must be written to
a non-volatile storage device prior to removing power if the
processor state is to be preserved. Writing b#00 to the FREQ bits
in the VR_CTL register also causes the EXT_WAKE signal to
transition low, which can be used to signal an external voltage
regulator to shut down.
Since VDDEXT is still supplied in this mode, all of the external sig-
nals three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to still have
power applied without drawing unwanted current.
The Ethernet module can signal an external regulator to wake
up using the EXT_WAKE signal. If PF15 does not connect as a
PHYINT signal to an external PHY device, it can be pulled low
by any other device to wake the processor up. The processor can
also be woken up by a real-time clock wakeup event or by assert-
ing the RESET pin. All hibernate wakeup events initiate the
hardware reset sequence. Individual sources are enabled by the
VR_CTL register. The EXT_WAKE signal is provided to indi-
cate the occurrence of wakeup events.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables may be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register controls
whether or not SDRAM operates in self-refresh mode, which
allows it to retain its content while the processor is in hiberna-
tion and through the subsequent reset sequence.
Power Savings
As shown in Table 3, the processors support up to six different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains, but all domains
must be powered according to the appropriate Specifications
table for processor Operating Conditions; even if the fea-
ture/peripheral is not used.
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock fre-
quency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
where the variables in the equations are:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
Table 3. Power Domains
Power Domain
VDD Range
All internal logic, except RTC, Memory, OTP
VDDINT
RTC internal logic and crystal I/O
VDDRTC
Memory logic
VDDMEM
OTP logic
VDDOTP
Optional internal flash
VDDFLASH
All other I/O
VDDEXT
Power Savings Factor
fCCLKRED
fCCLKNOM
--------------------------
VDDINTRED
VDDINTNOM
--------------------------------
2
×
TRED
TNOM
---------------
×
=
% Power Savings
1
Power Savings Factor
–
() 100%
×
=
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| ADSP-BF512FBSWZ-3 | 制造商:Analog Devices 功能描述: |
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