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參數(shù)資料
| 型號： | ADSP-BF512BSWZ-4 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/68頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16/32B 400MHZ LP 176LQFP |
| 標準包裝： | 40 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | I²C，PPI，SPI，SPORT，UART/USART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 116kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤 |
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Rev. B
|
Page 14 of 68
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January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 4 illustrates typical system clock ratios.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 5. This programmable core clock capability is useful for
fast core frequency modifications.
The maximum CCLK frequency not only depends on the part's
speed grade (see Page 65), it also depends on the applied VDDINT
voltage. See Table 9 for details. The maximal system clock rate
(SCLK) depends on the chip package and the applied VDDINT,
BOOTING MODES
The processor has several mechanisms (listed in Table 6) for
automatically loading internal and external memory after a
reset. The boot mode is defined by three BMODE input bits
dedicated to this purpose. There are two categories of boot
modes. In master boot modes the processor actively loads data
from parallel or serial memories. In slave boot modes the pro-
cessor receives data from external host devices.
The boot modes listed in Table 6 provide a number of mecha-
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time or
by proper OTP programming at pre-boot time. The BMODE
bits of the reset configuration register, sampled during power-
on resets and software-initiated resets, implement the modes
shown in Table 6.
Idle/no boot mode (BMODE = 0x0)—In this mode, the
processor goes into idle. The idle boot mode helps recover
from illegal operating modes, such as when the user has
mis configured the OTP memory.
Boot from 8-bit or 16-bit external flash memory
(BMODE = 0x1)—In this mode, the boot kernel loads the
first block header from address 0x2000 0000 and—depend-
ing on instructions containing in the header—the boot
kernel performs 8-bit or 16-bit boot or starts program exe-
cution at the address provided by the header. By default, all
configuration settings are set for the slowest device possible
(3-cycle hold time, 15-cycle R/W access times, 4-cycle
setup).
The ARDY is not enabled by default, but it can be enabled
by OTP programming. Similarly, all interface behavior and
timings can be customized by OTP programming. This
includes activation of burst-mode or page-mode operation.
In this mode, all signals belonging to the asynchronous
interface are enabled at the port muxing level.
Boot from internal SPI memory (BMODE = 0x2)—The
processor uses the internal PH8 GPIO signal to load code
previously loaded to the 4 Mbit internal SPI flash con-
nected to SPI0. Only available on the ADSP-BF512F/
ADSP-BF514F/ADSP-BF516F/ADSP-BF518F.
Boot from external SPI EEPROM or flash
(BMODE = 0x3)—8-bit, 16-bit, 24-bit or 32-bit address-
able devices are supported. The processor uses the PG15
GPIO signal (at SPI0SEL2) to select a single SPI
EEPROM/flash device connected to the SPI0 interface;
then submits a read command and successive address bytes
(0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device
is detected. Pull-up resistors are required on the SSEL and
MISO signals. By default, a value of 0x85 is written to the
SPI0_BAUD register.
Boot from SPI0 host device (BMODE = 0x4)—The proces-
sor operates in SPI slave mode and is configured to receive
the bytes of the LDR file from an SPI host (master) agent.
In the host, the HWAIT signal must be interrogated by the
Table 4. Example System Clock Ratios
Signal Name
SSEL3–0
Divider Ratio
VCO/SCLK
Example Frequency Ratios
(MHz)
VCO
SCLK
0010
2:1
100
50
0110
6:1
300
50
1010
10:1
400
40
Table 5. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
(MHz)
VCO
CCLK
00
1:1
300
01
2:1
300
150
10
4:1
400
100
11
8:1
200
25
Table 6. Booting Modes
BMODE2– 0 Description
000
Idle - No boot
001
Boot from 8- or 16-bit external flash memory
010
Boot from internal SPI memory
011
Boot from external SPI memory (EEPROM or flash)
100
Boot from SPI0 host
101
Boot from OTP memory
110
Boot from SDRAM
111
Boot from UART0 Host
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