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| 型號： | ADSP-BF512BSWZ-4 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/68頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16/32B 400MHZ LP 176LQFP |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | I²C，PPI，SPI，SPORT，UART/USART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 116kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤 |
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
|
Page 13 of 68
|
January 2011
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKRED
VOLTAGE REGULATION INTERFACE
The ADSP-BF51x processors require an external voltage regula-
tor to power the VDDINT domain. To reduce standby power
consumption in the hibernate state, the external voltage regula-
tor can be signaled through EXT_WAKE to remove power from
the processor core. The EXT_WAKE signal is high-true for
power-up and may be connected directly to the low-true shut
down input of many common regulators.
The Power Good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the PG functionality,
refer to the ADSP-BF51x Blackfin Processor Hardware Reference.
CLOCK SIGNALS
The ADSP-BF51x processors can be clocked by an external crys-
tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor CLKIN signal. When an external
clock is used, the XTAL pin/ball must be left unconnected.
Alternatively, because the processor includes an on-chip oscilla-
tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 4. A paral-
lel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins/balls. The
on-chip resistance between the CLKIN pin/ball and the XTAL
pin/ball is in the 500 kΩ range. Further parallel resistors are typ-
ically not recommended. The two capacitors and the series
resistor shown in Figure 4 fine tune phase and amplitude of the
sine frequency.
The capacitor and resistor values shown in Figure 4 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone oper-
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)—use site search on
“EE-168.”
The CLKBUF signal is an output signal, which is a buffered ver-
sion of the input clock. This signal is particularly useful in
Ethernet applications to limit the number of required clock
sources in the system. In this type of application, a single
25 MHz or 50 MHz crystal may be applied directly to the pro-
cessor. The 25 MHz or 50 MHz output of CLKBUF can then be
connected to an external Ethernet MII or RMII PHY device.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 5, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence.
On-the-fly frequency changes can be done simply by writing to
the PLL_DIV register. The maximum allowed CCLK and SCLK
rates depend on the applied voltages VDDINT, VDDEXT, and
VDDMEM, and the VCO is always permitted to run up to the fre-
quency specified by the part’s speed grade. The CLKOUT signal
reflects the SCLK frequency to the off-chip world. It belongs to
the SDRAM interface, but it functions as a reference signal in
other timing specifications as well. While active by default, it
can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL
registers.
Figure 4. External Crystal Connections
Figure 5. Frequency Modification Methods
CLKIN
CLKOUT
XTAL
EN
CLKBUF
TO PLL CIRCUITRY
FOR OVERTONE
OPERATION ONLY:
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0
.
18 pF *
EN
18 pF *
330
*
BLACKFIN
560
PLL
5
u to 64u
÷1 to 15
÷1,2, 4, 8
VCO
CLKIN
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
CCLK
SCLK
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| ADSP-BF512BSWZ-4F4 | 功能描述:IC DSP 16/32B 400MHZ LP 176LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF512FBSWZ-3 | 制造商:Analog Devices 功能描述: |
| ADSP-BF512FKBCZ-3 | 制造商:Analog Devices 功能描述: |
| ADSP-BF512KBCZ-3 | 功能描述:IC DSP 16/32B 300MHZ 168CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF512KBCZ-4 | 功能描述:IC DSP 16/32B 400MHZ 168CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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