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參數(shù)資料
| 型號(hào)： | ADSP-BF514BBCZ-4F4 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16/32B 400MHZ 168CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | I²C，PPI，RSI，SPI，SPORT，UART/USART |
| 時(shí)鐘速率： | 400MHz |
| 非易失內(nèi)存： | 閃存（4Mb） |
| 芯片上RAM： | 116kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 168-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 168-CSPBGA（12x12） |
| 包裝： | 托盤 |
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Rev. B
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Page 10 of 68
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January 2011
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
10/100 Ethernet MAC
The ADSP-BF516/ADSP-BF516F and ADSP-
BF518/ADSPBF518F processors offer the capability to directly
connect to a network by way of an embedded fast Ethernet
media access controller (MAC) that supports both 10-BaseT
(10M bits/sec) and 100-BaseT (100M bits/sec) operation. The
10/100 Ethernet MAC peripheral on the processor is fully com-
pliant to the IEEE 802.3-2002 standard and it provides
programmable features designed to minimize supervision, bus
use, or message processing by the rest of the processor system.
Some standard features are:
Support of MII and RMII protocols for external PHYs
Full duplex and half duplex modes
Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS
Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing
Flow control (in full-duplex operation): generation and
detection of pause frames
Station management: generation of MDC/MDIO frames
for read-write access to PHY registers
Operating range for active and sleep operating modes, see
Internal loopback from transmit to receive
Some advanced features are:
Buffered crystal output to external PHY for support of a
single crystal system
Automatic checksum computation of IP header and IP
payload fields of Rx frames
Independent 32-bit descriptor-driven receive and transmit
DMA channels
Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations
Convenient frame alignment modes support even 32-bit
alignment of encapsulated receive or transmit IP packet
data in memory after the 14-byte MAC header
Programmable Ethernet event interrupt supports any com-
bination of:
Selected receive or transmit frame status conditions
PHY interrupt condition
Wakeup frame detected
Selected MAC management counter(s) at half-full
DMA descriptor error
47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value
Programmable receive address filters, including a 64-bin
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames
Advanced power management supporting unattended
transfer of receive and transmit frames and status to/from
external memory via DMA during low power sleep mode
System wakeup from sleep operating mode upon magic
packet or any of four user-definable wakeup frame filters
Support for 802.3Q tagged VLAN frames
Programmable MDC clock rate and preamble suppression
In RMII operation, seven unused signals may be config-
ured as GPIO signals for other purposes
IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
ADSP-BF518/ADSP-BF518F processors include hardware sup-
port for IEEE 1588 with an integrated precision time protocol
synchronization engine (PTP_TSYNC). This engine provides
hardware assisted time stamping to improve the accuracy of
clock synchronization between PTP nodes. The main features of
the PTP_SYNC engine are:
Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
tocol standards
Hardware assisted time stamping capable of up to 12.5 ns
resolution
Lock adjustment
Programmable PTM message support
Dedicated interrupts
Programmable alarm
Multiple input clock sources (SCLK, MII clock, external
clock)
Programmable pulse per second (PPS) output
Auxiliary snapshot to time stamp external events
Ports
Because of the rich set of peripherals, the processors group the
many peripheral signals to four ports—port F, port G, port H,
and port J. Most of the associated pins/balls are shared by multi-
ple signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The ADSP-BF51x processors have 40 bidirectional, general-
purpose I/O (GPIO) signals allocated across three separate
GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associ-
ated with Port F, Port G, and Port H, respectively. Each
GPIO-capable signal shares functionality with other peripherals
via a multiplexing scheme; however, the GPIO functionality is
the default state of the device upon power-up. Neither GPIO
output nor input drivers are active by default. Each general-pur-
pose port signal can be individually controlled by manipulation
of the port control, status, and interrupt registers.
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| ADSP-BF514BSWZ-3 | 功能描述:IC DSP 16/32B 300MHZ LP 176LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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