參數(shù)資料
型號： ADSP-TS101SAB1Z000
廠商： Analog Devices Inc
文件頁數(shù)： 14/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 6MBIT 625-BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類型： 定點/浮點
接口： 主機接口，連接端口，多處理器
時鐘速率： 250MHz
非易失內(nèi)存： 外部
芯片上RAM： 768kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 625-BBGA
供應(yīng)商設(shè)備封裝： 625-PBGA（27x27）
包裝： 托盤
ADSP-TS101S
Rev. C
|
Page 21 of 48
|
May 2009
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 19 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD CAUTION
PACKAGE INFORMATION
The information presented in Figure 7 provide details about the
package branding for the ADSP-TS101S processors. For a com-
plete listing of product availability, see Ordering Guide on
TIMING SPECIFICATIONS
With the exception of link port, IRQ3–0, DMAR3–0, TMR0E,
FLAG3–0 (input), and TRST pins, all ac timing for the ADSP-
TS101S is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the ADSP-
TS101S has few calculated (formula-based) values. For informa-
tion on ac timing, see General AC Timing. For information on
link port transfer timing, see Link Ports Data Transfer and
General AC Timing
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 16 on Page 28. All delays (in nanoseconds)
are measured between the point that the first signal reaches
1.5 V and the point that the second signal reaches 1.5 V.
The ac asynchronous timing data for the IRQ3–0, DMAR3–0,
TMR0E, FLAG3–0 (input), and TRST pins appears in Table 21.
The general ac timing data appears in Table 21, Table 29, and
Table 30. All ac specifications are measured with the load speci-
fied in Figure 8, and with the output drive strength set to
strength 4. Output valid and hold are based on standard capaci-
tive loads: 30 pF on all pins. The delay and hold specifications
given should be derated by a drive strength related factor for
loads other than the nominal value of 30 pF.
In order to calculate the output valid and hold times for differ-
ent load conditions and/or output drive strengths, refer to
Fall Time vs. Load Capacitance) and Figure 40 on Page 36 (Out-
put Valid vs. Load Capacitance and Drive Strength).
Table 17. Absolute Maximum Ratings
Parameter
Rating
Internal (Core) Supply Voltage (VDDINT)
–0.3 V to +1.40 V
Analog (PLL) Supply Voltage (VDD_A)
–0.3 V to +1.40 V
External (I/O) Supply Voltage (VDDEXT)
–0.3 V to +4.6 V
Input Voltage
–0.5 V to V
DD
_IO + 0.5 V
Output Voltage Swing
–0.5 V to V
DD
_IO + 0.5 V
Storage Temperature Range
–65
C to +150C
Figure 7. Typical Package Brand
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
LLLLLLLLL-L 2.0
tppZ-ccc
T
ADSP-TS101S
a
yyww country_of_origin
vvvvv
Table 18. Package Brand Information
Brand Key
Field Description
t
Temperature Range
pp
Package Type
Z
Lead Free Option (optional)
ccc
See Ordering Guide
LLLLLLLLL-L
Silicon Lot Number
R.R
Silicon Revision
yyww
Date Code
vvvvvv
Assembly Lot Code
Figure 8. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
1.5V
TO
OUTPUT
PIN
30pF
50
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