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| 型號： | ADSP-TS101SAB1Z000 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/48頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 6MBIT 625-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點/浮點 |
| 接口： | 主機(jī)接口，連接端口，多處理器 |
| 時鐘速率： | 250MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 768kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 625-BBGA |
| 供應(yīng)商設(shè)備封裝： | 625-PBGA（27x27） |
| 包裝： | 托盤 |
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Rev. C
|
Page 10 of 48
|
May 2009
ADSP-TS101S
ates CCLK, which is phase-locked. The LCLKRAT pins
define the clock multiplication of LCLK to CCLK (see
Table 4). The link port clock is generated from CCLK via a
software programmable divisor. RESET must be asserted
until LCLK is stable and within specification for at least
2 ms. This applies to power-up as well as any dynamic
modification of LCLK after power-up. Dynamic modifica-
tion may include LCLK going out of specification as long as
RESET is asserted.
Connecting SCLK and LCLK to the same clock source is a
requirement for the device. Using an integer clock multiplica-
tion value provides predictable cycle-by-cycle operation, a
requirement of fault-tolerant systems and some multiprocessing
systems.
Noninteger values are completely functional and acceptable for
applications that do not require predictable cycle-by-cycle
operation.
OUTPUT PIN DRIVE STRENGTH CONTROL
Pins CONTROLIMP2–0 and DS2–0 work together to control
the output drive strength of two groups of pins, the
Address/Data/Control pin group and the Link pin group.
CONTROLIMP2–0 independently configures the two pin
groups to the maximum drive strength or to a digitally con-
trolled drive strength that is selectable by the DS2–0 pins (see
Table 13 on Page 18). If the digitally controlled drive strength is
selected for a pin group, the DS2–0 pins determine one of eight
strength levels for that group (see Table 14 on Page 18). The
drive strength selected varies the slew rate of the driver. Drive
strength 0 (DS2–0 = 000) is the weakest and slowest slew rate.
Drive strength 7 (DS2–0 = 111) is the strongest and fastest slew
rate.
The stronger drive strengths are useful for high frequency
switching while the lower strengths may allow use of a relaxed
design methodology. The strongest drive strengths have a larger
di/dt and thus require more attention to signal integrity issues
such a ringing, reflections and coupling. Also, a larger di/dt can
increase external supply rail noise, which impacts power supply
and power distribution design.
The drive strengths for the EMU, CPA, and DPA pins are not
controllable and are fixed to the maximum level.
For drive strength calculation, see Output Drive Currents on
POWER SUPPLIES
The ADSP-TS101S has separate power supply connections for
internal logic (VDD), analog circuits (VDD_A), and I/O buffer
(VDD_IO) power supply. The internal (VDD) and analog (VDD_A)
supplies must meet the 1.2 V requirement. The I/O buffer
(VDD_IO) supply must meet the 3.3 V requirement.
The analog supply (VDD_A) powers the clock generator PLLs. To
produce a stable clock, systems must provide a clean power sup-
ply to power input VDD_A. Designs must pay critical attention to
bypassing the VDD_A supply.
The required power-on sequence for the DSP is to provide VDD
(and VDD_A) before VDD_IO.
FILTERING REFERENCE VOLTAGE AND CLOCKS
LCLK_N. This circuit provides the reference voltage for the
switching voltage, system clock, and local clock references.
DEVELOPMENT TOOLS
The ADSP-TS101S is supported with a complete set of
CROSSCORE
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
devel-
opment environment. The same emulator hardware that
supports other TigerSHARC processors also fully emulates the
ADSP-TS101S.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ run-time library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The DSP has archi-
tectural features that improve the efficiency of compiled C/C++
code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and
efficiently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Figure 6. VREF, SCLK_N, and LCLK_N Filter
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
VDD_IO
VSS
VREF
SCLK_N
LCLK_N
R1
R2
C1
C2
R1: 2k
SERIES RESISTOR
R2: 1.67k
SERIES RESISTOR
C1: 1 F CAPACITOR (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
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