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| 型號： | ADSP-TS101SAB1Z000 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/48頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 6MBIT 625-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點(diǎn)/浮點(diǎn) |
| 接口： | 主機(jī)接口，連接端口，多處理器 |
| 時(shí)鐘速率： | 250MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 768kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 625-BBGA |
| 供應(yīng)商設(shè)備封裝： | 625-PBGA（27x27） |
| 包裝： | 托盤 |
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Rev. C
|
Page 12 of 48
|
May 2009
ADSP-TS101S
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS101S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. The
synchronous ac specification for asynchronous signals is used
only when predictable cycle-by-cycle behavior is required.
All inputs are sampled by a clock reference, therefore input
specifications (asynchronous minimum pulse widths or syn-
chronous input setup and hold) must be met to guarantee
recognition.
PIN STATES AT RESET
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these
pins to get to their internal pull-up or pull-down state. Some
output pins (control signals) have a pull-up or pull-down that
maintains a known value during transitions between different
drivers.
PIN DEFINITIONS
The Type column in the following pin definitions tables
describes the pin type, when the pin is used in the system. The
Term (for termination) column describes the pin termination
type if the pin is not used by the system. Note that some pins are
always used (indicated with au symbol).
Table 3. Pin Definitions—Clocks and Reset
Signal
Type
Term
Description
LCLK_N
I
au
LCLK_P
I
au
Local Clock Input. DSP clock input. The instruction cycle rate = n
LCLK, where n is user-
programmable to 2, 2.5, 3, 3.5, 4, 5, or 6. For more information, see Clock Domains on Page 9.
LCLKRAT2–0
1
I (pd
2)
au
LCLK Ratio. The DSP’s core clock (instruction cycle rate) = n
LCLK, where n is user-program-
mable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in Table 4. These pins must have a constant value while
the DSP is powered.
SCLK_N
I
au
SCLK_P
I
au
System Clock Input. The DSP’s system input clock for cluster bus. This pin must be connected
to the same clock source as LCLK_P. For more information, see Clock Domains on Page 9.
SCLKFREQ
3
I (pu
au
SCLK Frequency. SCLKFREQ = 1 is required. The SCLKFREQ pin must have a constant value while
the DSP is powered.
RESET
I/A
au
Reset. Sets the DSP to a known state and causes program to be in idle state. RESET must be
asserted at specified time according to the type of reset operation. For details, see Reset and
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
2 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances.
3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Table 4. LCLK Ratio
LCLKRAT2–0
Ratio
000
(default)
2
001
2.5
010
3
011
3.5
100
4
101
5
110
6
111
Reserved
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