- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19462 > ADSP-TS201SYBPZ050 (Analog Devices Inc)IC PROCESSOR 500MHZ 576-SBGA PDF資料下載
參數(shù)資料
| 型號： | ADSP-TS201SYBPZ050 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR 500MHZ 576-SBGA |
| 標準包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點/浮點 |
| 接口： | 主機接口，連接端口，多處理器 |
| 時鐘速率： | 500MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 3MB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 576-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 576-BGA-ED（25x25） |
| 包裝： | 托盤 |
| 配用： | ADZS-TS201S-EZLITE-ND - KIT LITE EVAL FOR ADSP-TS201S |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Rev. C
|
Page 12 of 48
|
December 2006
ADSP-TS201S
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS201S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. Use the ac
specification for asynchronous signals when the system design
requires predictable, cycle-by-cycle behavior for these signals.
The output pins can be three-stated during normal operation.
The DSP three-states all output pins during reset, allowing these
pins to get to their internal pull-up or pull-down state. Some
pins have an internal pull-up or pull-down resistor (±30% toler-
ance) that maintains a known value during transitions between
different drivers.
Table 3. Pin Definitions—Clocks and Reset
Signal
Type
Term
Description
SCLKRAT2–0
I (pd)
na
Core Clock Ratio. The DSP’s core clock (CCLK) rate = n × SCLK, where n is user-
programmable using the SCLKRATx pins to the values shown in Table 4. These pins
may change only during reset; connect these pins to VDD_IO or VSS. All reset specifica-
is the instruction cycle rate.
SCLK
I
na
System Clock Input. The DSP’s system input clock for cluster bus. The core clock rate
is user-programmable using the SCLKRATx pins. For more information, see Clock
RST_IN
I/A
na
Reset. Sets the DSP to a known state and causes program to be in idle state. RST_IN
must be asserted a specified time according to the type of reset operation. For details,
RST_OUT
O
na
Reset Output. Indicates that the DSP reset is complete. Connect to POR_IN.
POR_IN
I/A
na
Power-On Reset for internal DRAM. Connect to RST_OUT.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω to VSS; epu = external pull-up approx-
imately 5 k
Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS
Table 4. SCLK Ratio
SCLKRAT2–0
Ratio
000
(default)
4
001
5
010
6
011
7
100
8
101
10
110
12
111
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FAN2500S28X | IC REG LDO 2.8V .1A SOT-23-5 |
| 171-015-213R011 | CONN DB15 FEMALE DIP SLD NICKEL |
| VE-2WY-CW-F4 | CONVERTER MOD DC/DC 3.3V 66W |
| VE-2WR-CY-F4 | CONVERTER MOD DC/DC 7.5V 50W |
| TPSC106K020R0700 | CAP TANT 10UF 20V 10% 2312 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-TS202SABP-050 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 500MHz 500MIPS 576-Pin TEBGA 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT 500MHZ 500MIPS 576PIN TEBGA - Trays |
| ADSP-TS202SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS202SABP-X | 制造商:Analog Devices 功能描述: |
| ADSP-TS202SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-TS203SABP-050 | 功能描述:IC DSP FLOAT/FIXED 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復。