參數(shù)資料
型號(hào): ADT7463ARQ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: dB COOL Remote Thermal Controller and Voltage Monitor
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: MO-137AE, QSOP-24
文件頁數(shù): 29/53頁
文件大?。?/td> 719K
代理商: ADT7463ARQ
REV. 0
ADT7463
–29–
By reading the PWMx Current Duty Cycle Registers, you can
keep track of the current duty cycle on each PWM output, even
when the fans are running in Automatic Fan Speed Control
Mode or Acoustic Enhancement Mode.
VARY PWM DUTY
CYCLE WITH 8-BIT
RESOLUTION
Figure 37. Control PWM Duty Cycle Manually
with a Resolution of 0.39%
OPERATING FROM 3.3 V STANDBY
The ADT7463 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5
states, the core voltage of the processor will be lowered in these
states. If using the Dynamic T
MIN
Mode, lowering the core
voltage of the processor would change the CPU temperature
and change
the dynamics of the system under dynamic T
MIN
control.
Likewise, when monitoring
THERM
, the
THERM
timer
should be disabled during these states.
DYNAMIC T
MIN
CONTROL REGISTER 1 (REG. 0x36)
<1> V
CCP
LO = 1
When the power is supplied from 3.3 V STBY
and V
CCP
voltage drops below the V
CCP
Low Limit, the follow-
ing occurs:
Status Bit 1 (V
CCP
) in Status Register 1 gets set.
SMBALERT
gets generated if enabled.
THERM
monitoring is disabled. The
THERM
timer
should hold its value prior to the S3 or S5 state.
Dynamic T
MIN
control is disabled. This prevents T
MIN
from
being adjusted due to an S3 or S5 state.
The ADT7463 is prevented from entering the shutdown state.
Once the core voltage, V
CCP
, goes above the V
CCP
Low Limit, every-
thing gets re-enabled and the system resumes normal operation.
Note that since other voltages can drop or be turned off during
a low power state, these voltage channels will set status bits or
generate
SMBALERT
s. It is still necessary to mask out these
channels prior to entering a low power state using the Interrupt
Mask Registers. When exiting the low power state, the mask bits
can be cleared. This prevents the device from generating
unwanted
SMBALERT
s during the low power state.
XOR TREE TEST MODE
The ADT7463 includes an XOR Tree Test Mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XOR Tree, it is
possible to detect opens or shorts on the system board. Figure 38
shows the signals that are exercised in the XOR Tree Test Mode.
PWM1/XTO
PWM3
PWM2
TACH4
TACH3
TACH2
TACH1
VID4
VID3
VID2
VID1
VID0
Figure 38. XOR Tree Test
The XOR Tree Test is invoked by setting Bit 0 (XEN) of the
XOR Tree Test Enable Register (Reg. 0x6F).
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