參數(shù)資料
型號(hào): ADT7463ARQ
廠商: ANALOG DEVICES INC
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: dB COOL Remote Thermal Controller and Voltage Monitor
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: MO-137AE, QSOP-24
文件頁(yè)數(shù): 35/53頁(yè)
文件大?。?/td> 719K
代理商: ADT7463ARQ
REV. 0
ADT7463
–35–
Table XI. Register 0x37 – Dynamic T
MIN
Control Register 2 (Power-On Default = 0x00)
Bit
Name R/W
*
Description
<2:0>
CYR1
Read/Write
3-bit Remote 1 Cycle Value. These three bits define the delay time between making
subse-
quent T
MIN
adjustments in the control loop for Remote 1 channel, in terms of number of
monitoring cycles. The system will have associated thermal time constants that need to be
found to optimize the response of fans and the control loop.
BITS
000
001
010
011
100
101
110
111
DECREASE CYCLE
4 cycles (0.5 s)
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
INCREASE CYCLE
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
1024 cycles (128 s)
<5:3>
CYL
Read/Write
3-bit Local Temp Cycle Value. These three bits define the delay time between making subse-
quent T
MIN
adjustments in the control loop for Local Temp channel, in terms of number
of monitoring cycles. The system will have associated thermal time constants that need to
be found to optimize the response of fans and the control loop.
BITS
000
001
010
011
100
101
110
111
DECREASE CYCLE
4 cycles (0.5 s)
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
INCREASE CYCLE
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
1024 cycles (128 s)
<7:6>
CYR2
Read/Write
2 LSBs of 3-bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in Dynamic
T
MIN
Control Register 1 (Reg. 0x36).
These three bits define the delay time between making
subsequent T
MIN
adjustments in the control loop for Remote 2 channel, in terms of num-
ber of monitoring cycles. The system will have associated thermal time constants that
need to be found to optimize the response of fans and the control loop.
BITS
000
001
010
011
100
101
110
111
DECREASE CYCLE
4 cycles (0.5 s)
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
INCREASE CYCLE
8 cycles (1 s)
16 cycles (2 s)
32 cycles (4 s)
64 cycles (8 s)
128 cycles (16 s)
256 cycles (32 s)
512 cycles (64 s)
1024 cycles (128 s)
*
This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register will fail.
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