- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11203 > ADUC7032BSTZ-88-RL (Analog Devices Inc)IC MCU 96K FLASH DUAL 48LQFP PDF資料下載
參數(shù)資料
| 型號： | ADUC7032BSTZ-88-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 86/120頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁當前第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
ADuC7032-8L
Rev. A | Page 68 of 120
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It is used to service general-purpose interrupt
handling of internal and external events.
There are four 32-bit registers dedicated to IRQ.
IRQSIG
Reflects the status of the different IRQ sources. If a peripheral
generates an IRQ signal, the corresponding bit in the IRQSIG is
set; otherwise, it is cleared. The IRQSIG bits are cleared when the
interrupt in the particular peripheral is cleared. All IRQ sources
can be masked in the IRQEN MMR. IRQSIG is read only and can
be used to poll interrupt sources.
IRQEN
Provides the value of the current enable mask. When the bit is
set to 1, the source request is enabled to create an IRQ exception.
When the bit is set to 0, the source request is disabled or masked
and does not create an IRQ exception.
IRQCLR
A write-only register that allows clearing the IRQEN register to
mask an interrupt source. Each bit set to 1 clears the corresponding
bit in the IRQEN register without affecting the remaining bits.
The pair of registers, IRQEN and IRQCLR, allow independent
manipulation of the enable mask without requiring an auto-
matic read-modify-write.
IRQSTA
A read-only register that provides the current enabled IRQ source
status (effectively a Logic AND of the IRQSIG and IRQEN bits).
When the bit is set to 1, that source generates an active IRQ request
to the ARM7TDMI core. There is no priority encoder or interrupt
vector generation. This function is implemented in software in a
common interrupt handler routine. All 32 bits are logically OR’ed
to create a single IRQ signal to the ARM7TDMI core.
FIQ
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface, providing the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN, as a side effect, clears the same bit in IRQEN.
A bit set to 1 in IRQEN, as a side effect, clears the same bit in
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
Programmed Interrupts
Because the programmed interrupts are nonmaskable, they are
controlled by another register, SWICFG, which writes into both
IRQSTA and IRQSIG registers and/or FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG,
described in Table 52. This MMR allows the control of
programmed source interrupt.
Table 52. SWICFG MMR Bit Designations
Bit
Description
31 to 3
Reserved.
2
Programmed Interrupt FIQ.
Setting/clearing this bit corresponds to
setting/clearing Bit 1 of FIQSTA and FIQSIG.
1
Programmed Interrupt IRQ.
Setting/clearing this bit corresponds to
setting/clearing Bit 1 of IRQSTA and IRQSIG.
0
Reserved.
Note that to be detected by the interrupt controller and to be
detected by the user in the IRQSTA and FIQSTA registers, any
interrupt signal must be active for at least the minimum
interrupt latency time.
IR
QS
TA
FIQS
T
A
IR
QS
IG
FI
Q
S
IG
TIMER0
TIMER1
TIMER2
TIMER3
LIN H/W
FLASH/EE
PLL LOCK
ADC
UART
SPI
XIRQ
IR
QE
N
FI
Q
E
N
TIMER0
TIMER1
TIMER2
TIMER3
LIN H/W
FLASH/EE
PLL LOCK
ADC
UART
SPI
XIRQ
IRQ
FIQ
0
598
6-
0
29
Figure 29. Interrupt Structure
相關PDF資料 |
PDF描述 |
|---|---|
| AT91R40008-66AU-999 | IC MCU 32BIT RISC 100LQFP |
| ADUC7024BSTZ62-RL | IC MCU 12BIT 1MSPS UART 64-LQFP |
| VE-B33-IW-F3 | CONVERTER MOD DC/DC 24V 100W |
| VE-B33-IW-F1 | CONVERTER MOD DC/DC 24V 100W |
| VE-B34-IX-F3 | CONVERTER MOD DC/DC 48V 75W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC7032BSTZ-8L | 制造商:Analog Devices 功能描述:FLASH 96K ARM7 TRIPLE 16-BIT ADC LIN IC. - Trays |
| ADUC7032BSTZ-8L-RL | 制造商:Analog Devices 功能描述:FLASH 96K ARM7 TRIPLE 16-BIT ADC LIN IC. - Tape and Reel |
| ADUC7032BSTZ-8V | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| ADUC7032BSTZ-8V-RL | 功能描述:IC BATTERY SENSOR PREC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標準包裝:1,500 系列:AVR® ATtiny 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，LIN，SPI，UART/USART，USI 外圍設備:欠壓檢測/復位，POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):16 程序存儲器容量:8KB（4K x 16） 程序存儲器類型:閃存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉換器:A/D 11x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:帶卷 (TR) |
| ADUC7033 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Precision Battery Sensor For Automotive |
發(fā)布緊急采購，3分鐘左右您將得到回復。